NCP1219
PWM Controller with
Adjustable Skip Level and
External Latch Input
The NCP1219 represents a new, pin to pin compatible, generation
of the successful 7−pin current mode NCP12XX product series. The
controller allows for excellent standby power consumption by use of
its adjustable skip mode and integrated high voltage startup FET.
Internal frequency jittering, ramp compensation, timer−based fault
detection and a latch input make this controller an excellent
candidate for converters where ruggedness and component cost are
the key constraints.
The Dynamic Self Supply (DSS) drastically simplifies the
transformer design in avoiding the use of an auxiliary winding to
supply the NCP1219. This feature is particularly useful in
applications where the output voltage varies during operation (e.g.
battery chargers). Due to its high voltage technology, the IC can be
directly connected to the high voltage dc rail.
Features
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SOIC−7
D SUFFIX
CASE 751U
MARKING DIAGRAM
8
1219XZ
ALYW
G
1
•
Fixed−Frequency Current−Mode Operation with Ramp
•
•
•
•
•
•
•
•
•
•
•
•
Compensation (65 kHz and 100 kHz Options)
Dynamic Self Supply Eliminates the Need for an Auxiliary Winding
Timer−Based Fault Protection for Improved Overload Detection
Cycle Skip Reduces Input Power in Standby Mode
Latch and Auto−Recovery Overload Protection Options
Internal High Voltage Startup Circuit
Accurate Current Limit Detector (±5%)
Adjustable Skip Level
Latch Input for Easy Implementation of Overvoltage and
Overtemperature Protection
Frequency Modulation for Softened EMI Signature
500 mA/800 mA Peak Source/Sink Current Drive Capability
Pin to Pin Compatible with the Existing NCP12XX Series
These Devices are Pb−Free and Halogen Free/BFR Free*
1219 = Specific Device Code
X
= Overcurrent
=
(A = latch, B = auto−retry)
Z
= Frequency
=
(6 = 65 kHz, 1 = 100 kHz)
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
PIN CONNECTIONS
Skip/latch
FB
CS
GND
(Top View)
V
CC
Drv
1
HV
Typical Applications
•
AC−DC Adapters for Notebooks, LCD Monitors
•
Offline Battery Chargers
•
Consumer Electronic Appliances STB, DVD, DVDR
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 19 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques Reference
Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2009
October, 2009
−
Rev. 3
1
Publication Order Number:
NCP1219/D
NCP1219
+
AC
Input
EMI
Filter
Output
Voltage
−
latch input*
* Optional
Skip/latch HV
FB
V
CC
CS
GND
DRV
NCP1219
R
ramp
*
Figure 1. Typical Application Circuit
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2
NCP1219
2V
Skip/latch
R
upper
42.0k*
R
lower
51.3k*
V
Skip
V
Skip(max)
V
FB(open)
FB
V
FB
16.7k*
V
Skip/latch
Skip
Comparator
+
-
Soft−Start/PWM Clamp
V
latch
-
+
50
ms
*
filter
Latched overload
(Option A)
latch−off, reset when
V
CC
< V
CC(reset)
R
S
(Option A)
Q
I
start
when V
CC
> V
inhibit
I
inhibit
when V
CC
< V
inhibit
R
S
Q
+
-
V
CC(on)
TSD
-
+
Normal = V
CC(min)
Fault = V
CC(hiccup)
−
+
HV
R
skip
V
FB
/ 3
V
ILIM
t
SSTART
clamp
detect
time
soft−
start
set
75
ms*
filter
V
CC(reset)
UVLO
+
-
Fault
Management
Double Hiccup
Counter
V
CC
tOVLD
timer
reset
PWM
-
+
I
ramp(peak)
0
V
DD
CS
R
ramp
CS
R
CS
V
CS
I
ramp
LEB
Maximum
Duty Ratio
detect
Oscillator
R
S
disable
internal
bias
Q
V
CC
DRV
GND
7.5%* Jittering
* Typical values are shown
Figure 2. Functional Block Diagram
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3
NCP1219
Table 1. PIN FUNCTION DESCRIPTION
Pin
1
Name
Skip/latch
Description
This pin provides a latch input to permanently disable the device under a fault condition. It also allows the user to
adjust the skip threshold. A resistor between this pin and GND provides noise immunity to the latch input and sets
the skip threshold. The voltage on this pin is determined by the combination of the internal voltage divider and the
external resistor to ground. The default skip threshold is 1.1 V (typical) if no external resistor is used. An internal
clamp prevents the skip level from increasing above 1.3 V if the Skip/latch pin is pulled high to latch the controller.
The voltage on this pin is proportional to the output load on the converter. An internal resistor divider sets the
voltage on this pin above the regulation threshold (3 V) and an external optocoupler pulls the pin low to achieve
regulation. While the FB voltage is above its regulation threshold, the overload timer is enabled. If the overload
timer expires, the controller enters a double hiccup mode (option B) or is latched (option A) depending on the ver-
sion of the device. The converter enters skip mode if the FB voltage is below the skip threshold.
A voltage ramp proportional to the primary current is applied to this pin. The maximum current is reached once the
ramp voltage reaches 1 V (typical). A 100
mA
(typical) current source provides ramp compensation. The amount of
ramp compensation is adjusted with a series resistor between the CS pin and the current sense resistor.
Analog ground.
Main output of the PWM Controller. DRV has a source resistance of 12.6
W
(typical) and a sink resistance of 6.7
W
(typical).
Positive input supply. This pin connects to an external capacitor for energy storage. An internal current source
supplies current from the HV pin to this pin. Once the V
CC
voltage reaches V
CC(on)
(12.7 V typical), the current
source turns off and the DRV is enabled. The current source turns on once V
CC
falls to V
CC(min)
(9.9 V typical).
This mode of operation is known as dynamic self supply (DSS).
If the bias current consumption exceeds the startup current, and V
CC
drops 0.5 V (typical) below V
CC(min)
the con-
verter turns off and enters a double hiccup mode. If the V
CC
voltage is below 0.67 V (typical) the startup current is
reduced to 200
mA
(typical), reducing power dissipation.
This is the input of the high voltage startup regulator and connects directly to the bulk voltage. A controlled current
source supplies current from this pin to the V
CC
capacitor, eliminating the need for an external startup resistor. The
charge current is 12.8 mA (typical).
2
FB
3
CS
4
5
6
GND
DRV
VCC
8
HV
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NCP1219
Table 2. MAXIMUM RATINGS
(Notes 1
−
4)
Rating
HV Voltage
HV Current
Supply Voltage
Supply Current
Skip/latch Voltage
Skip/latch Current
FB Voltage
FB Current
CS Voltage
CS Current
DRV Voltage
DRV Current
Operating Junction Temperature
Storage Temperature Range
Power Dissipation (T
A
= 25°C, 2.0 Oz Cu, 1.0 Sq Inch Printed Circuit Copper Clad)
D Suffix, Plastic Package Case 751U (SOIC−7) (Note 4)
Thermal Resistance, Junction to Ambient (2.0 Oz Cu Printed Circuit Copper Clad)
D Suffix, Plastic Package Case 751U (SOIC−7)
Junction to Air, Low conductivity PCB (Note 3)
Junction to Lead, Low conductivity PCB (Note 3)
Junction to Air, High conductivity PCB (Note 4)
Junction to Lead, High conductivity PCB (Note 4)
Symbol
V
HV
I
HV
V
CC
I
CC
V
Skip/latch
I
Skip/latch
V
FB
I
FB
V
CS
I
CS
V
DRV
I
DRV
T
J
T
stg
P
D
Value
−0.3
to 500
100
−0.3
to 20
100
−0.3
to 9.5
100
−0.3
to 5.0
100
−0.3
to 5.0
100
−0.3
to 20
−500
to 800
–40 to 150
–60 to 150
0.92
Unit
V
mA
V
mA
V
mA
V
mA
V
mA
V
mA
°C
°C
W
°C/W
R
θJA
R
θJL
R
θJA
R
θJL
177
75
136
69
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. This device series contains ESD protection and exceeds the following tests:
Pins 1– 6: Human Body Model 3000 V per JEDEC JESD22−A114−F
.
Pins 1– 6:
Machine Model Method 300 V per JEDEC JESD22−A115−A.
Pin 8 is the HV startup of the device and is rated to the maximum rating of the part, or 500 V.
2. This device contains Latch−Up protection and exceeds
±100
mA per JEDEC Standard JESD78.
3. As mounted on a 40x40x1.5 mm FR4 substrate with a single layer of 80 mm
2
of 2 oz copper traces and heat spreading area. As specified for
a JEDEC 51 low conductivity test PCB. Test conditions were under natural convection or zero air flow.
4. As mounted on a 40x40x1.5 mm FR4 substrate with a single layer of 650 mm
2
of 2 oz copper traces and heat spreading area. As specified
for a JEDEC 51 high conductivity test PCB. Test conditions were under natural convection or zero air flow.
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