NBXSBA021, NBXSBB021
3.3 V, 266.667 MHz LVPECL
Clock Oscillator
The NBXSBB021/NBXSBA021 single frequency crystal oscillator
(XO) is designed to meet today's requirements for 3.3 V LVPECL
clock generation applications. The device uses a high Q fundamental
crystal and Phase Lock Loop (PLL) multiplier to provide
266.667 MHz, ultra low jitter and phase noise LVPECL differential
output.
This device is a member of ON Semiconductor's PureEdget clock
family that provides accurate and precision clock solutions.
Available in 5 mm x 7 mm SMD (CLCC) package on 16 mm tape
and reel in quantities of 1,000. Frequency stability options available as
either 50 PPM NBXSBA021 or 20 PPM NBXSBB021.
Features
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6 PIN CLCC
LN SUFFIX
CASE 848AB
•
•
•
•
•
•
•
•
LVPECL Differential Output
Uses High Q Fundamental Mode Crystal and PLL Multiplier
Ultra Low Jitter and Phase Noise - 0.4 ps (12 kHz - 20 MHz)
Output Frequency - 266.667 MHz
Hermetically Sealed Ceramic SMD Package
RoHS Compliant
Operating Range 3.3 V
±10%
Total Frequency Stability -
±20
PPM or
±50
PPM
MARKING DIAGRAMS
NBXSBB021
266.667
AWLYYWW
NBXSBA021
266.667
AWLYYWW
Applications
•
Servers
•
Fully Buffered DIMM
NBXSBB021 = NBXSBB021 (±20 PPM)*
NBXSBA021 = NBXSBA021 (±50 PPM)
266.667
= Output Frequency (MHz)
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
ORDERING INFORMATION
V
DD
6
CLK CLK
5 4
Device
NBXSBB021LN1TAG*
NBXSBA021LN1TAG
Crystal
PLL
Clock
Multiplier
Package
CLCC-6
(Pb-Free)
CLCC-6
(Pb-Free)
Shipping
†
1000/
Tape & Reel
1000/
Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
3
GND
* Please contact sales office for availability
1
OE
2
NC
Figure 1. Simplified Logic Diagram
©
Semiconductor Components Industries, LLC, 2008
1
May, 2008 - Rev. 1
Publication Order Number:
NBXSBB021/D
NBXSBA021, NBXSBB021
OE
1
6
V
DD
NC
2
5
CLK
GND
3
4
CLK
Figure 2. Pin Connections
(Top View)
Table 1. PIN DESCRIPTION
Pin No.
1
2
3
4
5
6
Symbol
OE
NC
I/O
LVTTL/LVCMOS
Control Input
N/A
Description
Output Enable Pin. When left floating pin defaults to logic HIGH and output is active.
See OE pin description Table 2.
No Connect.
Ground 0 V.
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GND
CLK
CLK
V
DD
Power Supply
LVPECL Output
LVPECL Output
Power Supply
Non-Inverted Clock Output. Typically loaded with 50
W
receiver termination resistor to
V
TT
= V
DD
- 2 V.
Inverted Clock Output. Typically loaded with 50
W
receiver termination resistor to
V
TT
= V
DD
- 2 V.
Positive power supply voltage. Voltage should not exceed 3.3 V
±10%.
Table 2. OUTPUT ENABLE TRI-STATE FUNCTION
OE Pin
Open
HIGH Level
LOW Level
Output Pins
Active
Active
High Z
Table 3. ATTRIBUTES
Characteristic
Internal Default State Resistor
ESD Protection
Human Body Model
Machine Model
Value
170 kW
2 kV
200 V
Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test
1. For additional Moisture Sensitivity information, refer to Application Note AND8003/D.
Table 4. MAXIMUM RATINGS
Symbol
V
DD
I
out
T
A
T
stg
T
sol
Parameter
Positive Power Supply
LVPECL Output Current
Operating Temperature Range
Storage Temperature Range
Wave Solder
See Figure 5
Condition 1
GND = 0 V
Continuous
Surge
Condition 2
Rating
4.6
25
50
-40 to +85
-55 to +120
260
Units
V
mA
°C
°C
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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NBXSBA021, NBXSBB021
Table 5. DC CHARACTERISTICS
(V
DD
= 3.3 V
±
10%, GND = 0 V, T
A
= -40°C to +85°C) (Note 2)
Symbol
I
DD
V
IH
V
IL
I
IH
I
IL
V
OH
V
OL
V
OUTPP
Characteristic
Power Supply Current (Note 2)
OE Input HIGH Voltage
OE Input LOW Voltage
Input HIGH Current
Input LOW Current
Output HIGH Voltage (Note 2)
V
DD
= 3.3 V
Output LOW Voltage (Note 2)
V
DD
= 3.3 V
Output Voltage Amplitude (Note 2)
OE
OE
2000
GND - 300
-100
-100
V
DD
-1195
2105
V
DD
-1945
1355
700
Conditions
Min.
Typ.
75
Max.
100
V
DD
800
+100
+100
V
DD
-945
2355
V
DD
-1600
1700
Units
mA
mV
mV
mA
mA
mV
mV
mV
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 Ifpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
2. Measurement taken with outputs terminated with 50 ohm to V
DD
-2 V. See Figure 4.
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NBXSBA021, NBXSBB021
Table 6. AC CHARACTERISTICS
(V
DD
= 3.3 V
±
10%, GND = 0 V, T
A
= -40°C to +85°C) (Note 3)
Symbol
f
CLKOUT
Df
Characteristic
Output Clock Frequency
Frequency Stability - NBXSBB021
Frequency Stability
- NBXSBA021
Phase-Noise Performance
f
CLKout
= 266.667 MHz
0°C to +70°C
-40°C to +85°C
(Note 4)
100 Hz of Carrier
1 kHz of Carrier
10 kHz of Carrier
100 kHz of Carrier
1 MHz of Carrier
10 MHz of Carrier
t
jit
(F)
t
jitter
RMS Phase Jitter
Cycle to Cycle, RMS
Cycle to Cycle, Peak-to-Peak
Period, RMS
Period, Peak-to-Peak
t
OE/OD
t
DUTY_CYCLE
t
R
t
F
t
start
Output Enable/Disable Time
Output Clock Duty Cycle
(Measured at Cross Point)
Output Rise Time (20% and 80%)
Output Fall Time (80% and 20%)
Start-up Time
Aging
1
st
Year
Every Year After 1
st
48
50
250
250
1
12 kHz to 20 MHz
1000 Cycles
1000 Cycles
10,000 Cycles
10,000 Cycles
-102
-114
-123
-123
-132
-157
0.4
1.5
10
1
7
0.9
8
30
4
20
200
52
400
400
5
3
1
Conditions
Min.
Typ.
266.667
±20
±50
Max.
Units
MHz
PPM
F
NOISE
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
ps
ps
ps
ps
ps
ns
%
ps
ps
ms
ppm
ppm
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 Ifpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
3. Measurement taken with outputs terminated with 50 ohm to V
DD
-2 V. See Figure 4.
4. Parameter guarantees 10 years of aging. Includes initial stability at 25°C, shock, vibration, and first year aging.
Figure 3. Typical Phase Noise Plot
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NBXSBA021, NBXSBB021
Table 7. RELIABILITY COMPLIANCE
Parameter
Shock
Mechanical
Mechanical
Mechanical
Mechanical
Standard
Method
MIL-STD-833, Method 2002, Condition B
MIL-STD-833, Method 2003
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Solderability
Vibration
MIL-STD-833, Method 2007, Condition A
MIL-STD-202, Method 215
Solvent Resistance
Thermal Shock
Environment
Environment
MIL-STD-833, Method 1011, Condition A
Moisture Level Sensitivity
MSL1 260°C per IPC/JEDEC J-STD-020D
NBXSBB021/NBXSBA021
CLK
Driver
Device
CLK
Z
o
= 50
W
50
W
50
W
V
TT
V
TT
= V
DD
- 2.0 V
D
Z
o
= 50
W
D
Receiver
Device
Figure 4. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D - Termination of ECL Logic Devices.)
Temperature (°C)
260
217
temp. 260°C
20 - 40 sec. max.
peak
3°C/sec. max.
6°C/sec. max.
ramp-up
175
150
cooling
pre-heat
reflow
Time
60180 sec.
60150 sec.
Figure 5. Recommended Reflow Soldering Profile
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