NBXDPA012
2.5 V / 3.3 V, 106.25 MHz /
212.5 MHz LVDS Clock
Oscillator
The NBXDPA012 dual frequency crystal oscillator (XO) is
designed to meet today’s requirements for 2.5 V and 3.3 V LVDS
clock generation applications. The device uses a high Q fundamental
crystal and Phase Lock Loop (PLL) multiplier to provide selectable
106.25 MHz or 212.5 MHz, ultra low jitter and phase noise LVDS
differential output.
This device is a member of ON Semiconductor’s PureEdget clock
family that provides accurate and precision clock solutions.
Available in 5 mm x 7 mm SMD (CLCC) package on 16 mm tape
and reel in quantities of 1000.
Features
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MARKING DIAGRAM
NBXDPA012
106.25/212.5
AAWLYYWWG
6 PIN CLCC
LN SUFFIX
CASE 848AB
NBXDPA012
106.25/212.5
AA
WL
YY
WW
G or
G
•
•
•
•
•
•
•
LVDS Differential Output
Uses High Q Fundamental Mode Crystal and PLL Multiplier
Ultra Low Jitter and Phase Noise
−
0.4 ps (12 kHz
−
20 MHz)
Selectable Output Frequency
−
106.25 MHz (default) / 212.5 MHz
Hermetically Sealed Ceramic SMD Package
RoHS Compliant
Operating Range: 2.5 V
±5%
Operating Range:
3.3 V
±10%
•
Total Frequency Stability
−
$50
ppm
•
This is a Pb−Free Device
Applications
= NBXDPA012 (±50 PPM)
= Output Frequency (MHz)
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
Device
NBXDPA012LN1TAG
NBXDPA012LNHTAG
Package
CLCC−6
(Pb−Free)
CLCC−6
(Pb−Free)
Shipping
†
1000/
Tape & Reel
100/
Tape & Reel
•
1x and 2x Fiber Channel
•
Host Bus Adapter
V
DD
6
CLK CLK
5 4
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Crystal
PLL
Clock
Multiplier
1
OE
2
FSEL
3
GND
Figure 1. Simplified Logic Diagram
©
Semiconductor Components Industries, LLC, 2009
October, 2009
−
Rev. 1
1
Publication Order Number:
NBXDPA012/D
NBXDPA012
OE
FSEL
GND
1
2
3
6
5
4
V
DD
CLK
CLK
Figure 2. Pin Connections
(Top View)
Table 1. PIN DESCRIPTION
Pin No.
1
2
3
4
5
6
Symbol
OE
I/O
LVTTL/LVCMOS
Control Input
LVTTL/LVCMOS
Control Input
Power Supply
LVDS Output
LVDS Output
Description
Output Enable Pin. When left floating pin defaults to logic HIGH and output is active.
See OE pin description Table 2.
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Á
Á Á
FSEL
GND
CLK
CLK
V
DD
Output Frequency Select Pin. Pin will default to logic HIGH when left open. See Output
Frequency Select pin description Table 3.
Ground 0 V
Non−Inverted Clock Output. Typically loaded with 100
W
receiver termination resistor
across differential pair.
Inverted Clock Output. Typically loaded with 100
W
receiver termination resistor across
differential pair.
Positive power supply voltage. Voltage should not exceed 2.5 V
±5%
or 3.3 V
±10%.
Power Supply
Table 2. OUTPUT ENABLE TRI−STATE FUNCTION
OE Pin
Open
HIGH Level
LOW Level
Output Pins
Active
Active
High Z
Table 3. OUTPUT FREQUENCY SELECT
FSEL Pin
Open
(pin will float high)
HIGH Level
LOW Level
Output Frequency (MHz)
106.25
106.25
212.5
Table 4. ATTRIBUTES
Characteristic
Input Default State Resistor
ESD Protection
Human Body Model
Machine Model
Value
170 kW
2 kV
200 V
Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test
1. For additional Moisture Sensitivity information, refer to Application Note AND8003/D.
Table 5. MAXIMUM RATINGS
Symbol
V
DD
I
out
T
A
T
stg
T
sol
Parameter
Positive Power Supply
LVDS Output Current
Operating Temperature Range
Storage Temperature Range
Wave Solder
See Figure 6
Condition 1
GND = 0 V
Continuous
Surge
Condition 2
Rating
4.6
25
50
−40
to +85
−55
to +120
260
Units
V
mA
°C
°C
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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NBXDPA012
Table 6. DC CHARACTERISTICS
(V
DD
= 2.5 V
±
5% or V
DD
= 3.3 V
±
10%, GND = 0 V, T
A
=
−40°C
to +85°C) (Note 2)
Symbol
I
DD
V
IH
V
IL
I
IH
I
IL
DV
OD
Characteristic
Power Supply Current
OE and FSEL Input HIGH Voltage
OE and FSEL Input LOW Voltage
Input HIGH Current
Input LOW Current
OE
FSEL
OE
FSEL
2000
GND
−
300
−100
−100
−100
−100
0
1
Conditions
Min.
Typ.
85
Max.
105
V
DD
800
+100
+100
+100
+100
25
Units
mA
mV
mV
mA
mA
mV
Change in Magnitude of V
OD
for
Complementary Output States
(Note 3)
Offset Voltage
Change in Magnitude of V
OS
for
Complementary Output States
(Note 3)
Output HIGH Voltage
Output LOW Voltage
Differential Output Voltage
V
DD
= 2.5 V
V
DD
= 3.3 V
V
DD
= 2.5 V
V
DD
= 3.3 V
V
OS
DV
OS
1125
0
1
1375
25
mV
mV
V
OH
V
OL
V
OD
1425
900
250
1075
1600
mV
mV
450
mV
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 Ifpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
2. Measurement taken with outputs terminated with 100 ohm across differential pair. See Figure 5.
3. Parameter guaranteed by design verification not tested in production.
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NBXDPA012
Table 7. AC CHARACTERISTICS
(V
DD
= 2.5 V
±
5% or V
DD
= 3.3 V
±
10%, GND = 0 V, T
A
=
−40°C
to +85°C) (Note 4)
Symbol
f
CLKOUT
Df
F
NOISE
Characteristic
Output Clock Frequency
Frequency Stability
−
NBXDPA012
Phase−Noise Performance
f
CLKout
= 106.25 MHz/212.5 MHz
(See Figures 3 and 4)
Conditions
FSEL = HIGH
FSEL = LOW
(Note 5)
100 Hz of Carrier
1 kHz of Carrier
10 kHz of Carrier
100 kHz of Carrier
1 MHz of Carrier
10 MHz of Carrier
t
jit
(F)
t
jitter
RMS Phase Jitter
Cycle to Cycle, RMS
Cycle to Cycle, Peak−to−Peak
Period, RMS
Period, Peak−to−Peak
t
OE/OD
t
DUTY_CYCLE
t
R
t
F
t
start
Output Enable/Disable Time
Output Clock Duty Cycle
(Measured at Cross Point)
Output Rise Time (20% and 80%)
Output Fall Time (80% and 20%)
Start−up Time
Aging
1
st
Year
Every Year After 1
st
48
50
115
115
1
12 kHz to 20 MHz
1000 Cycles
1000 Cycles
10,000 Cycles
10,000 Cycles
−112/−105
−123/−116
−131/−124
−131/−124
−139/−133
−161/−158
0.4
3
7
2
10
0.75
8
35
4
20
200
52
400
400
5
3
1
Min.
Typ.
106.25
212.5
±50
ppm
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
ps
ps
ps
ps
ps
ns
%
ps
ps
ms
ppm
ppm
Max.
Units
MHz
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 Ifpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. Measurement taken with outputs terminated with 100 ohm across differential pair. See Figure 5.
5. Parameter guarantees 10 years of aging. Includes initial stability at 25°C, shock, vibration and first year aging.
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NBXDPA012
Figure 3. Typical Phase Noise Plot at 106.25 MHz
Figure 4. Typical Phase Noise Plot at 212.5 MHz
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