NB7L585R
2.5V/3.3V, 7GHz/10Gbps
Differential 2:1 Mux Input to
1:6 RSECL Clock/Data
Fanout Buffer / Translator
Multi−Level Inputs w/ Internal
Termination
Description
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MARKING
DIAGRAM
1
The NB7L585R is a differential 1:6 RSECL Clock/Data distribution
chip featuring a 2:1 Clock/Data input multiplexer with an input select
pin. The INx/INx inputs incorporate internal 50
W
termination
resistors and will accept LVPECL, CML, or LVDS logic levels.
The NB7L585R produces six identical output copies of Clock or
Data operating up to 7 GHz or 10 Gb/s, respectively. As such,
NB7L585R is ideal for SONET, GigE, Fiber Channel, Backplane and
other Clock/Data distribution applications.
The NB7L585R is powered with either 2.5 V or 3.3 V supply and is
offered in a low profile 5mm x 5mm 32−pin QFN package.
Application notes, models, and support documentation are available
at www.onsemi.com.
The NB7L585R is a member of the GigaComm™ family of high
performance clock products.
Features
1
32
QFN32
MN SUFFIX
CASE 488AM
NB7L
585R
AWLYYWWG
G
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
+
SEL
Q0
VREFAC0
IN0
VT0
IN0
50
W
50
W
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Maximum Input Data Rate > 10 Gb/s Typical
Data Dependent Jitter < 10 ps
Maximum Input Clock Frequency > 7 GHz Typical
Random Clock Jitter < 0.8 ps RMS
Low Skew 1:6 RSECL Outputs, 20 ps max
2:1 Multi−Level Mux Inputs
160 ps Typical Propagation Delay
40 ps Typical Rise and Fall Times
Differential RSECL Outputs, 400 mV peak−to−peak, typical
Operating Range: V
CC
= 2.375 V to 3.6 V with GND = 0 V
Internal 50
W
Input Termination Resistors
VREFAC Reference Output
QFN−32 Package, 5mm x 5mm
−40ºC
to +85ºC Ambient Operating Temperature
These Devices are Pb−Free and are RoHS Compliant
Q0
Q1
0
Q1
Q2
IN1
VT1
IN1
Q2
Q3
50
W
50
W
1
Q3
Q4
VREFAC1
V
CC
GND
Q4
Q5
Q5
Figure 1. Simplified Block Diagram
ORDERING INFORMATION
See detailed ordering and shipping information on page 8 of
this data sheet.
©
Semiconductor Components Industries, LLC, 2009
1
October, 2009
−
Rev. 0
Publication Order Number:
NB7L585R/D
NB7L585R
GND
VCC
VCC
SEL
Q0
Q0
Q1
Q1
Exposed
Pad (EP)
Table 1. INPUT SELECT FUNCTION TABLE
SEL*
0
CLK Input Selected
IN0
IN1
32
IN0
VT0
VREFAC0
IN0
IN1
VT1
VREFAC1
IN1
1
2
3
4
5
6
7
8
9
GND
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
GND
VCC
Q2
Q2
Q3
Q3
VCC
GND
1
*Defaults HIGH when left open.
NB7L585R
10
NC
11
VCC
12
Q5
13
Q5
14
Q4
15
Q4
16
VCC
Figure 2. Pinout: QFN−32 (Top View)
Table 2. PIN DESCRIPTION
Pin Number
1,4
5,8
2,6
31
10
11, 16, 18
23, 25, 30
29, 28
27, 26
22, 21
20, 19
15, 14
13, 12
9, 17, 24, 32
3
7
−
Pin Name
IN0, IN0
IN1, IN1
VT0, VT1
SEL
NC
V
CC
Q0, Q0
Q1, Q1
Q2,Q2
Q3, Q3
Q4, Q4
Q5, Q5
GND
VREFAC0
VREFAC1
EP
−
−
LVTTL/LVCMOS
Input
−
−
RSECL Output
I/O
LVPECL, CML,
LVDS Input
Pin Description
Non−inverted, Inverted, Differential Data Inputs internally biased to V
CC
/2
Internal 100
W
Center−tapped Termination Pin for IN0 / IN0 and IN1 / IN1
Input Select pin; LOW for IN0 Inputs, HIGH for IN1 Inputs; defaults HIGH when left
open
No Connect
Positive Supply Voltage. All V
CC
pins must be connected to the positive power supply
for correct DC and AC operation.
Non−inverted, Inverted Differential Outputs Note 1.
Negative Supply Voltage, connected to Ground
Output Voltage Reference for Capacitor−Coupled Inputs
The Exposed Pad (EP) on the QFN−32 package bottom is thermally connected to the
die for improved heat transfer out of package. The exposed pad must be attached to a
heat−sinking conduit. The pad is electrically connected to the die, and must be elec-
trically and thermally connected to GND on the PC board.
1. In the differential configuration when the input termination pins (VT0, VT1) are connected to a common termination voltage or left open, and
if no signal is applied on INn/INn input, then the device will be susceptible to self−oscillation.
2. All V
CC
and GND pins must be externally connected to a power supply for proper operation.
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NB7L585R
Table 3. ATTRIBUTES
Characteristics
ESD Protection
R
PU
−
SEL Input Pullup Resistor
Moisture Sensitivity (Note 3)
Flammability Rating
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
3. For additional information, see Application Note AND8003/D.
QFN−32
Oxygen Index: 28 to 34
Human Body Model
Machine Model
Value
> 2 kV
> 200 V
37.5 kW
Level 1
UL 94 V−0 @ 0.125 in
303
Table 4. MAXIMUM RATINGS
Symbol
V
CC
V
IO
V
INPP
I
IN
I
out
I
VREFAC
T
A
T
stg
q
JA
q
JC
T
sol
Positive Power Supply
Input/Output Voltage
Differential Input Voltage |IN
−
IN|
Input Current Through R
T
(50
W
Resistor)
Output Current
VREFAC Sink or Source Current
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient) (Note 4)
Thermal Resistance (Junction−to−Case) (Note 4)
Wave Solder
0 lfpm
500 lfpm
QFN32
QFN32
QFN32
Continuous
Surge
Parameter
Condition 1
GND = 0 V
GND = 0 V
Condition 2
Rating
+4.0
−0.5
to V
CC
+0.5
1.89
$40
50
100
$1.5
−40
to +85
−65
to +150
31
27
12
265
Unit
V
V
V
mA
mA
mA
°C
°C
°C/W
°C/W
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
4. JEDEC standard multilayer board
−
2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
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NB7L585R
Table 5. DC CHARACTERISTICS POSITIVE RSECL OUTPUT
V
CC
= 2.375 V to 3.6 V; GND = 0 V; T
A
=
−40°C
to 85°C (Note 5)
Symbol
POWER SUPPLY
V
CC
I
CC
V
OH
Power Supply Voltage
Power Supply Current (Inputs and Outputs Open)
V
CC
= 3.3V
V
CC
= 2.5V
3.0
2.375
3.3
2.5
185
3.6
2.625
225
V
mA
Characteristic
Min
Typ
Max
Unit
RSECL Outputs
Output HIGH Voltage (Note 6)
V
CC
= 3.3 V
V
CC
= 2.5 V
V
CC
= 3.3 V
V
CC
= 2.5 V
V
CC
– 1300
2000
1200
V
CC
– 1800
1500
700
V
CC
– 1125
2175
1375
V
CC
– 1525
1775
975
V
CC
– 1000
2300
1500
V
CC
– 1350
1950
1150
mV
V
OL
Output LOW Voltage (Note 6)
mV
DIFFERENTIAL CLOCK INPUTS DRIVEN SINGLE−ENDED
(Note 7) (Figures 5 & 6)
V
IH
V
IL
V
th
V
ISE
V
REFAC
Single−ended Input HIGH Voltage
Single−ended Input LOW Voltage
Input Threshold Reference Voltage Range (Note 8)
Single−ended Input Voltage (V
IH
−
V
IL
)
Output Reference Voltage @100
mA
for Capacitor− Coupled
Inputs, Only
V
th
+ 100
GND
1100
200
V
CC
V
th
−
100
V
CC
−100
V
CC
– GND
V
CC
– 1150
V
CC
– 1000
mV
mV
mV
mV
VREFACx
(for Capacitor− Coupled Inputs, Only)
V
CC
– 1350
mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY
(Figures 7 & 8) (Note 9)
V
IHD
V
ILD
V
ID
V
CMR
I
IH
I
IL
V
IH
V
IL
I
IH
I
IL
R
TIN
Differential Input HIGH Voltage (IN, IN)
Differential Input LOW Voltage (IN , IN)
Differential Input Voltage (IN , IN) (V
IHD
−
V
ILD
)
Input Common Mode Range (Differential Configuration, Note 10)
(Figure 9)
Input HIGH Current IN/IN (VTIN/VTIN Open)
Input LOW Current IN/IN (VTIN/VTIN Open)
1200
GND
100
1050
−150
−150
V
CC
V
IHD
−
100
1200
V
CC
−
50
150
150
mV
mV
mV
mV
mA
mA
CONTROL INPUT
(SEL Pin)
Input HIGH Voltage for Control Pin
Input LOW Voltage for Control Pin
Input HIGH Current
Input LOW Current
2.0
GND
−150
−150
V
CC
0.8
150
150
mV
mV
mA
mA
TERMINATION RESISTORS
Internal Input Termination Resistor (Measured from INx to VTx)
45
50
55
W
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Input and output parameters vary 1:1 with V
CC
.
6. RSECL outputs (Qn/Qn) loaded with 50
W
to V
CC
– 2 V for proper operation.
7. V
th
, V
IH
, V
IL,,
and V
ISE
parameters must be complied with simultaneously.
8. V
th
is applied to the complementary input when operating in single−ended mode.
9. V
IHD
, V
ILD,
V
ID
and V
CMR
parameters must be complied with simultaneously.
10. V
CMR
min varies 1:1 with GND, V
CMR
max varies 1:1 with V
CC
. The V
CMR
range is referenced to the most positive side of the differential
input signal.
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NB7L585R
Table 6. AC CHARACTERISTICS
V
CC
= 2.375 V to 3.6 V; GND = 0 V; T
A
=
−40°C
to 85°C (Note 11)
Symbol
f
MAX
f
DATAMAX
f
SEL
V
OUTpp
t
PLH
,
t
PHL
t
PLH
TC
tskew
t
DC
F
N
Characteristic
Maximum Input Clock Frequency; V
OUTpp
w
200 mV
Maximum Operating Data Rate (PRBS23)
Maximum Toggle Frequency, SEL
Output Voltage Amplitude (@ V
INPPmin
)
(Note 12) (Figures 8 and 10)
Propagation Delay to Differential Outputs, @ 1 GHz,
measured at differential crosspoint
Propagation Delay Temperature Coefficient
Output
−
Output skew (within device) (Note 13)
Device
−
Device skew (tpd max – tpdmin)
Output Clock Duty Cycle (Reference Duty Cycle = 50%)
Phase Noise, f
c
= 1 GHz
f
in
v
6.0 GHz
10 kHz
100 kHz
1 MHz
10 MHz
20 MHz
40 MHz
45
50
−134
−136
−149
−150
−150
−151
36
0.2
2.0
0.8
10
0.7
100
15
40
1200
70
f
in
≤
6.0 GHz
IN/IN to Q/Q
SEL to Q
Min
6
8
1.0
200
100
Typ
7
10
1.5
400
160
200
50
20
100
55
225
300
Max
Unit
GHz
Gbps
GHz
mV
ps
Dfs/°C
ps
%
dBc
t
FN
t
JITTER
Integrated Phase Jitter (Figure x) f
c
= 1 GHz, 12 kHz
*
20 MHz Offset (RMS)
RJ – Output Random Jitter (Note 14)
DJ
−
Residual Output Deterministic Jitter (Note 15)
Crosstalk Induced Jitter (Adjacent Channel) (Note 17)
f
in
≤
5.0 GHz
≤
8 Gbps
fs
ps RMS
ps pk−pk
ps RMS
mV
ps
V
INPP
t
r,
, t
f
Input Voltage Swing (Differential Configuration) (Note 16)
Output Rise/Fall Times @ 1 GHz (20%
−
80%), Q, Q
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
11. Measured using a 400 mV pk−pk source, 50% duty cycle clock source. All output loading with external 50
W
to V
CC
– 2 V. Input edge
rates 40 ps (20%
−
80%).
12. Output voltage swing is a single−ended measurement operating in differential mode.
13. Skew is measured between outputs under identical transitions and conditions. Duty cycle skew is defined only for differential operation when
the delays are measured from cross−point of the inputs to the crosspoint of the outputs.
14. Additive RMS jitter with 50% duty cycle clock signal.
15. Additive Peak−to−Peak data dependent jitter with input NRZ data at PRBS23.
16. Input voltage swing is a single−ended measurement operating in differential mode.
17. Crosstalk is measured at the output while applying two similar clock frequencies that are asynchronous with respect to each other at the
inputs.
500
OUTPUT VOLTAGE AMPLITUDE
(mV)
Q AMP (mV)
400
300
200
100
0
0
1
2
3
4
5
6
7
8
Figure 3. Clock Output Voltage Amplitude (V
OUTpp
) vs. Input Frequency (f
in
) at Ambient Temperature (Typical)
f
in
, CLOCK INPUT FREQUENCY (GHz)
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