NB6LQ572
2.5V / 3.3V Differential 4:1
Mux w/Input Equalizer to
1:2 LVPECL Clock/Data
Fanout / Translator
Multi−Level Inputs w/ Internal Termination
The NB6LQ572 is a high performance differential 4:1 Clock/Data
input multiplexer and a 1:2 LVPECL Clock / Data fanout buffer that
operates up to 5 GHz / 6.5 Gbps respectively with a 2.5 V or 3.3 V
power supply.
Each INx/INx input pair incorporates a fixed Equalizer Receiver,
which when placed in series with a Clock / Data path, will enhance the
degraded signal transmitted across an FR4 backplane or cable
interconnect. For applications that do not require Equalization,
consider the NB6L572, which is pin−compatible to the NB6LQ572.
The differential Clock / Data inputs have internal 50
W
termination
resistors and will accept differential LVPECL, CML, or LVDS logic
levels. The NB6LQ572 incorporates a pair of Select pins that will
choose one of four differential inputs and will produce two identical
LVPECL output copies of Clock or Data. As such, the NB6LQ572 is
ideal for SONET, GigE, Fiber Channel, Backplane and other
Clock/Data distribution applications.
The two differential LVPECL outputs will swing 750 mV when
externally loaded and terminated with a 50
W
resistor to V
CC
– 2 V
and are optimized for low skew and minimal jitter.
The NB6LQ572 is offered in a low profile 5x5 mm 32−pin QFN
Pb−Free package. Application notes, models, and support
documentation are available at www.onsemi.com.
The NB6LQ572 is a member of the ECLinPS MAX™ family of
high performance clock products.
Features
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MARKING
DIAGRAM
1
1
32
QFN32
MN SUFFIX
CASE 488AM
NB6L
Q572
AWLYYWWG
G
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information on page 9 of
this data sheet.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
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Input Data Rate > 6.5 Gb/s Typical
Data Dependent Jitter < 10 ps
Maximum Input Clock Frequency > 5 GHz Typical
Random Clock Jitter < 0.8ps RMS
Fixed Input Equalization
Low Skew 1:2 LVPECL Outputs, < 15 ps max
4:1 Multi−Level Mux Inputs, accepts LVPECL, CML LVDS
150ps Typical Propagation Delay
55ps Typical Rise and Fall Times
Differential LVPECL Outputs, 800 mV peak−to−peak, typical
Operating Range: V
CC
= 2.375 V to 3.6 V
Internal 50
W
Input Termination Resistors
V
REFAC
Reference Output
QFN−32 Package, 5mm x 5mm
−40°C
to +85°C Ambient Operating Temperature
These are Pb−Free Devices
©
Semiconductor Components Industries, LLC, 2009
1
April, 2009
−
Rev. 0
Publication Order Number:
NB6LQ572/D
NB6LQ572
Multilevel Inputs
LVPECL, LVDS, CML
IN0
VT0
IN0
50
W
50
W
EQ0
0
VREFAC0
IN1
VT1
IN1
50
W
50
W
LVPECL OUTPUTS
Q0
Q0
4:1 MUX
EQ1
1
VREFAC1
IN2
VT2
IN2
50
W
50
W
EQ2
2
Q1
Q1
VREFAC2
IN3
VT3
IN3
50
W
50
W
EQ3
3
VREFAC3
SEL0
SEL1
Figure 1. Simplified Block Diagram
VREFAC3
VREFAC2
VT3
VT2
IN3
IN3
IN2
IN2
Exposed
Pad (EP)
Table 1. Input Select Function Table
SEL1*
0
SEL0*
0
1
0
1
Clock / Data Input Selected
IN0 Input Selected
IN1 Input Selected
IN2 Input Selected
IN3 Input Selected
32
IN0
VT0
VREFAC0
IN0
IN1
VT1
VREFAC1
IN1
1
2
3
4
5
6
7
8
9
GND
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
GND
VCC
Q1
Q1
VCC
NC
SEL1
VCC
0
1
1
*Defaults HIGH when left open.
10
VCC
11
Q0
12
Q0
13
VCC
14
NC
15
SEL0
16
VCC
Figure 2. Pinout: QFN−32 (Top View)
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2
NB6LQ572
Table 2. PIN DESCRIPTION
Pin Num-
ber
1, 4
5, 8
25, 28
29, 32
2, 6
26, 30
15
18
14, 19
10, 13, 16
17, 20, 23
11, 12
21, 22
9, 24
3
7
27
31
−
Pin Name
IN0, IN0
IN1, IN1
IN2, IN2
IN3, IN3
VT0, VT1
VT2, VT3
SEL0
SEL1
NC
V
CC
Q0, Q0
Q1, Q1
GND
VREFAC0
VREFAC1
VREFAC2
VREFAC3
EP
−
LVTTL/LVCMOS
Input
−
−
LVPECL Output
I/O
LVPECL, CML,
LVDS Input
Pin Description
Noninverted, Inverted, Differential Clock or Data Inputs
Internal 100
W
Center−tapped Termination Pin for INx / INx
Input Select pins, default HIGH when left open through a 94 kW pullup resistor.
Input logic threshold is V
CC
/ 2. See Select Function, Table 1.
No Connect
Positive Supply Voltage.
Non−inverted, Inverted Differential Outputs.
Negative Supply Voltage
Output Voltage Reference for Capacitor−Coupled Inputs
−
The Exposed Pad (EP) on the QFN−32 package bottom is thermally connected to
the die for improved heat transfer out of package. The exposed pad must be
attached to a heat−sinking conduit. The pad is electrically connected to the die, and
must be electrically connected to GND.
1. In the differential configuration when the input termination pins (VT0, VT1, VT2, VT3) are connected to a common termination voltage or
left open, and if no signal is applied on INx/INx input, then the device will be susceptible to self−oscillation.
2. All V
CC
and GND pins must be externally connected to a power supply for proper operation.
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3
NB6LQ572
Table 3. ATTRIBUTES
Characteristics
ESD Protection
R
PU
−
SELx Input Pull−up Resistor
Moisture Sensitivity (Note 3)
Flammability Rating
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
3. For additional information, see Application Note AND8003/D.
QFN−32
Oxygen Index: 28 to 34
Human Body Model
Machine Model
Value
> 2 kV
> 200 V
94 kW
Level 1
UL 94 V−0 @ 0.125 in
221
Table 4. MAXIMUM RATINGS
Symbol
V
CC
V
IN
V
INPP
I
OUT
I
IN
I
VREFAC
T
A
T
stg
q
JA
q
JC
T
sol
Positive Power Supply
Positive Input Voltage
Differential Input Voltage |IN – IN|
LVPECL Output Current
Input current Through RT (50
W
resistor)
V
REFAC
Sink or Source Current
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient) (Note 4)
Thermal Resistance (Junction−to−Case) (Note 4)
Wave Solder
v
20 sec
0 lfpm
500 lfpm
QFN−32
QFN−32
QFN−32
Continuous
Surge
Parameter
Condition 1
GND = 0 V
GND = 0 V
Condition 2
Rating
−0.5
to +4.0
−0.5
to V
CC
+0.5
1.89
50
100
$40
$1.5
−40
to +85
−65
to +150
31
27
12
265
Unit
V
V
V
mA
mA
mA
°C
°C
°C/W
°C/W
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
4. JEDEC standard multilayer board – 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
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NB6LQ572
Table 5. DC CHARACTERISTICS POSITIVE LVPECL OUTPUT
V
CC
= 2.375 V to 3.6 V, GND = 0 V, T
A
=
−40°C
to +85°C
Symbol
POWER SUPPLY
V
CC
I
CC
V
OH
Power Supply Voltage
V
CC
= 2.5 V
V
CC
= 3.3 V
2.375
3.0
2.5
3.3
75
2.625
3.6
110
V
mA
Characteristic
Min
Typ
Max
Unit
(Note 5)
Power Supply Current for V
CC
(Inputs and Outputs Open)
Output HIGH Voltage (Note 6)
V
CC
– 1145
1355
2155
V
CC
– 2000
500
1300
LVPECL OUTPUTS
V
CC
= 2.5 V
V
CC
= 3.3 V
V
CC
= 2.5 V
V
CC
= 3.3 V
V
CC
– 900
1600
2400
V
CC
−
1700
800
1600
V
CC
– 800
1700
2500
V
CC
– 1500
1000
1800
mV
V
OL
Output LOW Voltage (Note 6)
mV
DIFFERENTIAL CLOCK INPUTS DRIVEN SINGLE−ENDED
(Note 7) (Figures 5 and 6)
V
IH
V
IL
V
th
V
ISE
VREFAC
V
REFAC
V
IHD
V
ILD
V
ID
V
CMR
I
IH
I
IL
V
IH
V
IL
I
IH
I
IL
R
TIN
Output Reference Voltage (100
mA
Load)
V
CC
– 1300
1200
0
100
1150
−150
−150
V
CC
– 1100
V
CC
– 900
V
CC
V
IHD
– 100
1200
V
CC
– 50
150
150
mV
Single−ended Input HIGH Voltage
Single−ended Input LOW Voltage
Input Threshold Reference Voltage Range (Note 8)
Single−ended Input Voltage (V
IH
– V
IL
)
V
th
+ 100
GND
1100
200
V
CC
V
th
– 100
V
CC
– 100
1200
mV
mV
mV
mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY
(Note 9) (Figures 7 and 8)
Differential Input HIGH Voltage (IN
x
, IN
x
)
Differential Input LOW Voltage (IN
x
, IN
x
)
Differential Input Voltage (IN
x
, IN
x
) (V
IHD
– V
ILD
)
Input Common Mode Range (Differential Configuration)
(Note 10) (Figure 9)
Input HIGH Current IN
x
/IN
x
(VT
x
/VT
x
Open)
Input LOW Current IN
x
/IN
x
(VT
x
/VT
x
Open)
Input HIGH Voltage for Control Pin
Input LOW Voltage for Control Pin
Input HIGH Current
Input LOW Current
mV
mV
mV
mV
mA
mA
V
V
mA
mA
CONTROL INPUT
(SELx Pin)
2.0
GND
−150
−150
V
CC
0.8
150
150
TERMINATION RESISTORS
Internal Input Termination Resistor (Measured from INx to VTx)
45
50
55
W
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Input and Output parameters vary 1:1 with V
CC
.
6. LVPECL outputs loaded with 50
W
to V
CC
−
2 V for proper operation.
7. Vth, V
IH
, V
IL,,
and V
ISE
parameters must be complied with simultaneously.
8. Vth is applied to the complementary input when operating in single−ended mode.
9. V
IHD
, V
ILD,
V
ID
and V
CMR
parameters must be complied with simultaneously.
10. V
CMR
min varies 1:1 with GND, V
CMR
max varies 1:1 with V
CC
. The V
CMR
range is referenced to the most positive side of the differential
input signal.
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