Metal Oxide Varistors
SMD Multilayer Varistor Array with Ni-Barrier Termination
Preliminary data sheet
(parameters may be changed if necessary)
CA04P2S14THSG
B72762A8140S160
Designation System
CA
04
P
2
S
14
T
HS
G
=
Chip Array
= Dimensions of the device
04x05
(Length x width in 1/100 inch)
= Design (Parallel internal structure)
= Number of elements
= Special Tolerance of the varistor voltage
= Max. operating voltage
=
Three
layer termination (Ni-barrier)
= Designed for protection of
High Speed
data lines
= Taped version, cardboard tape, 7" reel (5000 pcs/reel)
Figure
l
b
l = 1,37 ± 0,15
b = 1,0 + 0/ -0,15
s = 0,70 max.
d = 0,36 ± 0,1
e
Ref
= 0,64
d
s
(All dimensions in mm)
e
As far as patents or other rights of third parties are concerned, liability is only assumed for components per se, not for
applications, processes and circuits implemented within components or assemblies. The information describes the type of
component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved.
ISSUE DATE
08.07.02
ISSUE
c
PUBLISHER
KB VS PE
PAGE
1/7
Metal Oxide Varistors
SMD Multilayer Varistor Array with Ni-Barrier Termination
Preliminary data sheet
(parameters may be changed if necessary)
CA04P2S14THSG
B72762A8140S160
V-I-Characteristic
200
V
v
100
80
60
40
VAR9733A
20
10
8
6
4
2
1
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
i
A 10
1
Max. current, energy, operating voltage and average power
dissipation depending on ambient temperature
%
100
90
80
70
60
50
40
30
20
10
0
-55
70
80
90
100 110 120
Ambient temperature
130
140
150 °C
ISSUE DATE
08.07.02
ISSUE
c
PUBLISHER
KB VS PE
PAGE
2/7
Metal Oxide Varistors
SMD Multilayer Varistor Array with Ni-Barrier Termination
Preliminary data sheet
(parameters may be changed if necessary)
CA04P2S14THSG
B72762A8140S160
Electrical Data
Max. operating voltage
RMS voltage
DC voltage
Varistor voltage (@ 1 mA)
Max. clamping voltage (@ 1 A)
Max. average power dissipation
Max. surge current (8/20 µs)
Max. energy absorption (ESD)
(@ ESD acc. IEC61000-4-2;
15kV Air Discharge, 150pF, 330
Ω)
Capacitance
1
Veff = 14 V
VDC = 16 V
VV = 23 - 33 V
VC = 66 V
Pmax = 3 mW
Îmax = 1 x 2 A
Emax = 30mJ
C = 10pF
1
measured @ 1 MHz, 1 V, 25°C, typical value
Response time
Operating temperature
Storage temperature (mounted parts)
Termination material
< 0.5 ns
-40 ... +85 °C
-40 ... +125 °C
Ag/Ni/Sn
(thickness not specified, adjusted to fulfill wettability specification acc. to
IEC 60068-2-58)
Application Note
The described component is designed to meet
acc. IEC61000-4-2 (8kV contact discharge 150pF, 330
Ω).
ESD
level
4
requirements
ISSUE DATE
08.07.02
ISSUE
c
PUBLISHER
KB VS PE
PAGE
3/7
Metal Oxide Varistors
SMD Multilayer Varistor Array with Ni-Barrier Termination
Preliminary data sheet
(parameters may be changed if necessary)
CA04P2S14THSG
B72762A8140S160
Signal Insertion Loss
1
0
-2
-4
-6
-8
-10
-12
-14
-16
-18
-20
0
50
100
150
frequency [MHz]
200
250
300
1
typical values; measured with network analyzer HP8753 E/S containing s-parameter test set
Stability to Multiple ESD-Discharges
2
40
30
20
10
0
0
1
10
100
1000
10000
number of ESD pulses
2
(8kV contact discharge; 150pF, 330
Ω
; acc. IEC 61000-4-2).
ISSUE DATE
08.07.02
ISSUE
c
PUBLISHER
KB VS PE
PAGE
4/7
Metal Oxide Varistors
SMD Multilayer Varistor Array with Ni-Barrier Termination
Preliminary data sheet
(parameters may be changed if necessary)
CA04P2S14THSG
B72762A8140S160
Recommended Geometry of Solder Pads
A = 0,4 mm
B = 0,55 mm
C = 0,28 mm
E = 0,64 mm
E
B
C
A
Recommended Soldering Temperature Profiles
300
°C
250
T
200
150
100
max 2°C/s
50
0
0
50
100
150
t
200
s
250
~ 245 °C
215 °C
180 °C
~ 40 s
~ 100 s
This component is suited for IR-soldering.
Max. reflow cycles: 2x
As far as possible, the components shall be employed within 6 months. They should be left in
their original packings to avoid soldering problems due to oxidized contacts.
Storage temperature: -25 to 45°C.
Relative humidity: <75% annual average, <95% on max. 30 days in a year.
The usage of mild, non activated fluxes for soldering is recommended, as well as proper
cleaning of the PCB.
ISSUE DATE
08.07.02
ISSUE
c
PUBLISHER
KB VS PE
PAGE
5/7
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