COMMUNICATIONS MODULES & SUBSYSTEMS
OC-12 SFP Transceiver (Multirate, 1310 nm and 1550 nm)
CT2 Series
Key Features
• SFP MSA compatible
• Fully OC-12 SONET compliant at all reaches: IR-1, LR-1,
and LR-2
• Microprocessor-based design fully implements the
Digital Diagnostic Monitoring Interface
• Automatic output power and extinction ratio control
over temperature and lifetime to compensate for laser
efficiency degradation
• Expandable options, such as a custom software user interface
Applications
• Metro access
• Metro core
• Wide area networks
The JDSU CT2 Series OC-12 (622 Mb/s) transceiver module integrates optics and
electronics in a Small Form Factor Pluggable (SFP) package. It is Multisource
Agreement (MSA) compatible and designed for operation at 1310 nm and 1550
nm. Although optimized for OC-12, it provides multirate capability and can be
used at OC-3 (155 Mb/s).
The CT2 Series SFP transceiver provides a fully OC-12 SONET compliant
interface between the SONET/SDH photonic layer and the electrical layer. Its
microprocessor-based modular design implements all features specified in the
SFP MSA compatible 2-wire Serial Digital Diagnostic Monitoring Interface for
Optical Transceivers.
The major components in this module include a Fabry-Perot or uncooled
distributed feedback (DFB) based optical transmitter, a PIN based optical receiver
with integrated transimpedence amplifier (TIA), a microprocessor, a limiting post
amplifier, and a laser driver. The modular transceiver design offers a "hot
pluggable" interface, allowing the same basic architecture to be used for IR-1, LR-1,
and LR-2 versions.
Compliance
• GR-253-CORE
• ITU-T G.957
• SFF-8472
NORTH AMERICA
:
800 498-JDSU (5378)
WORLDWIDE
:
+800 5378-JDSU
WEBSITE
:
www.jdsu.com
OC-12 SFP TRANSCEIVER
2
Dimensions Diagram
(Specifications in mm unless otherwise noted; see dimensions table on next page.)
K REF
J MIN
A
A
F REF
D
F REF
A
M
C
P
N
Y MAX
B
H MAX
L MIN X 45°
Y MAX
G REF
Section A-A
S
R MAX
See Detail Y
Q
W
T
U
X REF
V
AG
AF
AA REF
AE REF
Z
Z
Z
AB MAX
Detail Y
Section Z-Z
OC-12 SFP TRANSCEIVER
3
Dimension Table for the CT2
Designator
A
B
C
D
E
F
G
H
J
K
L
M
N
P
Q
R
S
T
U
V
W
X
Y
Z
AA
AB
AE
Dimension
13.7 mm
8.6 mm
8.5 mm
13.4 mm
1.0 mm
2.3 mm
4.2 mm
2.0 mm
28.5 mm
55.0 mm
1.1 mm x 45°
2.0 mm
2.25 mm
1.0 mm
9.2 mm
0.7 mm
45.0 mm
34.6 mm
41.8 mm
2.7 mm
2.7 mm
7.3 mm
2.0 mm
0.45 mm
8.6 mm
2.6 mm
6.0 mm
Tolerance
±0.1 mm
±0.1 mm
±0.1 mm
±0.1 mm
Maximum
Reference
Reference
Maximum
Minimum
Reference
Minimum
±0.25 mm
±0.1 mm
±0.1 mm
±0.1 mm
Maximum
±0.2 mm
±0.3 mm
±0.15 mm
±0.05 mm
±0.1 mm
Reference
Maximum
±0.05 mm
Reference
Maximum
Reference
Comments
Transceiver width, nose piece or front that extends inside cage
Transceiver height, front, that extends inside cage
Transceiver height, rear
Transceiver width, rear
Extension of front sides outside of cage
Location of cage grounding springs from centerline, top
Location of side cage grounding springs from top
Width of cage grounding springs
Location of transition between nose piece and rear of transceiver
Transceiver overall length
Chamfer on bottom of housing
Height of rear shoulder from transceiver printed circuit board
Location of printed circuit board to bottom of transceiver
Thickness of printed circuit board
Width of printed circuit board
Width of skirt in rear of transceiver
Length from latch shoulder to rear of transceiver
Length from latch shoulder to bottom opening of transceiver
Length from latch shoulder to end of printed circuit board
Length from latch shoulder to shoulder of transceiver outside of cage
(location of positive stop)
Clearance for actuator tines
Transceiver length extending outside of cage
Maximum length of top and bottom transceiver extending outside of cage
Height of latch boss
Transceiver height, front, that extends inside the cage
Length of latch boss
Width of cavity that contains the actuator
Bail Latch Color Code Definition
Bail Latch Color
Yellow
Red
White
Wavelength
1310 nm
1310 nm
1550 nm
Typical Reach
IR (15 km)
LR (40 km)
LR (80 km)
OC-12 SFP TRANSCEIVER
4
CT2 Electrical Pad Layout
20
19
18
17
16
15
14
13
12
11
VeeT
TD-
TD+
VeeT
VccT
VccR
VeeR
RD+
RD-
VeeR
1
2
3
4
5
6
7
8
9
10
VeeT
Tx Fault
Tx Disable
MOD-DEF(2)
MOD-DEF(1)
MOD-DEF(0)
Rate Select
LOS
VeeR
VeeR
Top of Board
Bottom of Board (As Viewed
through Top of Board)
Transceiver Pin Descriptions
Pin
TD
TDb
RD
RDb
Rate_select
TxDIS
LOS
Description
Un-clocked, multirate, differential serial bit stream (155 Mb/s to 622 Mb/s) used to drive the optical transmitter.
Internally AC coupled and terminated via internal 100
Ω
differential impedence.
Differential received electrical signal capable of detecting 155 Mb/s to 622 Mb/s bit patterns.
The differential pair is internally biased and AC coupled. This signal requires 100
Ω
external differential termination.
Internally monitored and available for future use. Can be customized for specific applications.
Transmitter Disable Input. A logic HIGH on this input pin disables the transmitter's laser so that there is no optical
output. If left open the transmitter will be disabled.
Loss of Signal (Open Collector). A logic HIGH on this output indicates an incoming signal level that is less than
-32 dBm but no greater than -38 dBm. LOS shall deassert (logic LOW) when a 3 dB (maximum), 0.5 dB (minimum)
hysteresis is obtained.
Transmitter fault (Open collector). A logic HIGH indicates that the transmitter is in a fault condition.
MOD_DEF(0) is internally grounded to indicate the presence of the module. Must be pulled-up on host board with
a 10 KΩ resistor.
MOD_DEF(1) is the clock of the 2 wire interface for module monitoring.
MOD_DEF(2) is the data line of the 2 wire interface for module monitoring.
Receiver, Transmitter power supply, respectively
Receiver, Transmitter ground, respectively. The chassis ground and circuit ground isolation is configurable.
Tx_fault
MOD_DEF(0)
MOD_DEF(1)
MOD_DEF(2)
VccR, VccT
VeeR, VeeT
OC-12 SFP TRANSCEIVER
5
Absolute Maximum Ratings
Parameter
Extended operating case temperature range
Storage case temperature range
Supply voltage
Voltage on any input/output pin
High-speed output source current
Lead soldering temperature/time
Operating relative humidity (non-condensing)
Receiver optical input power (PIN)
Minimum
-40 °C
-40 °C
-0.5 V
0V
-
-
5%
-
Maximum
85 °C
85 °C
4.0 V
Vcc
50 mA
250 °C/10 seconds
85%
3 dBm
Transceiver Electrical Input/Output Characteristics
(Vcc = 3.3 V±5%)
Parameter
Input data signal levels input voltage swing, DVIN (internally AC coupled)
Transmitter disable input (disabled/enabled)
Rate select input (high data rate/low data rate)
Transmitter fault output (asserted/deasserted)
Output data signal levels
1
output voltage swing, DVOUT (internally AC coupled)
Loss-of-signal output (output high, VOH/output low, VOL)
Minimum
200 mV
2.0 V/0 V
2.8 V/0 V
2.4 V/0 V
400 mV
2.4 V/0 V
Maximum
2000 mV
Vcc/0.8 V
Vcc/0.6 V
Vcc/0.5 V
2000 mV
Vcc/0.5 V
1. Terminated into 100
Ω
differential. These levels are guaranteed down to 2 dB lower than the typical receiver sensitivity for each data rate and reach.
FPGA/CPLD
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