MDT2005(JG)
1. General Description
This EPROM-Based 8-bit micro-controller
uses a fully static CMOS design
technology combines higher speeds and
smaller size with the low power and high
noise immunity of CMOS.
On chip memory system includes 0.5 K(for
MDT2005) bytes of ROM, and 32 bytes of
static RAM.
Power-on Reset (POR), only available
while PED is Disable
Power edge-detector Reset (PED)
Sleep Mode for power saving
8-bit real time clock/counter(RTCC)
with 8-bit programmable prescaler
4 types of oscillator can be selected
by programming option:
RC－Low cost RC oscillator
LFXT－Low frequency crystal
oscillator
XTAL－Standard crystal oscillator
HFXT－High frequency crystal
oscillator
4 oscillator start-up time can be
selected by programming option:
150
µs,
20 ms, 40 ms, 80 ms
On-chip RC oscillator based
Watchdog Timer(WDT) can be operated
freely
12 I/O pins with their own independent
direction control
2. Features
The followings are some of the features
on the hardware and software :
Fully CMOS static design
8-bit data bus
On chip ROM size : 512 words for
MDT2005
Internal RAM size : 32 bytes
(25 general purpose registers, 7 special
registers)
36 single word instructions
14-bit instructions
2-level stacks
Operating voltage : 2.3V ~ 6.0 V
Operating frequency : 0 ~ 20 MHz
The most fast execution time is 200
ns under 20 MHz in all single cycle
instructions
except
the
branch
instruction
Addressing modes include direct,
indirect and relative addressing modes
3. Applications
The application areas of this MDT2005
range from appliance motor control and
high speed automotive to low power
remote transmitters/receivers, pointing
devices,
and
telecommunications
processors, such as Remote controller,
small
instruments,
chargers,
toy,
automobile and PC peripheral … etc.
This specification are subject to be changed without notice. Any latest information
http;//www.mdtic.com.tw
please preview
P. 1
2006/4
VER1.1
MDT2005(JG)
4. Pin Assignment
DIP / SOP
PA2 1
18 PA1
PA3
RTCC
/MCLR
V
ss
PB0
PB1
PB2
PB3
2
3
4
5
6
7
8
9
17
16
15
14
13
12
11
10
PA0
OSC1
OSC2
V
dd
PB7
PB6
PB5
PB4
SSOP
PA2
PA3
RTCC
/MCLR
VSS
VSS
PB0
PB1
PB2
PB3
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
PA1
PA0
OSC1
OSC2
VDD
VDD
PB7
PB6
PB5
PB4
5. Pin Function Description
Pin Name
PA0~PA3
PB0~PB7
RTCC
/MCLR
OSC1
OSC2
V
dd
V
ss
I/O
I/O
I/O
I
I
I
O
Function Description
Port A, TTL input level
Port B, TTL input level
Real Time Clock/Counter, Schmitt Trigger input levels
Master Clear, Schmitt Trigger input levels
Oscillator Input
Oscillator Output
Power supply
Ground
This specification are subject to be changed without notice. Any latest information
http;//www.mdtic.com.tw
please preview
P. 2
2006/4
VER1.1
MDT2005(JG)
6. Memory Map
(A) Register Map
Address
00
01
02
03
04
05
06
07~1F
Description
Indirect Addressing Register
RTCC
PC
STATUS
MSR
Port A
Port B
Internal RAM, General Purpose Register
(1) IAR ( Indirect Address Register) : R0
(2) RTCC (Real Time Counter/Counter Register) : R1
(3) PC (Program Counter) : R2
Write PC, CALL --- always 0
LJUMP, JUMP, LCALL --- from instruction word
RTWI, RET --- from STACK
A9
A8
A7~A0
Write PC, JUMP, CALL --- always 0 (ROM 0.5K)
LJUMP, LCALL --- from instruction word
RTWI, RET --- from STACK
Write PC --- from ALU
LJUMP, JUMP, LCALL, CALL --- from instruction word
RTWI, RET --- from STACK
This specification are subject to be changed without notice. Any latest information
please preview http;//www.mdtic.com.tw
P. 2
2006/4
VER1.1
MDT2005(JG)
(4) STATUS (Status register) : R3
Bit
0
1
2
3
4
5-7
Symbol
C
HC
Z
PF
TF
——
Carry bit
Half Carry bit
Zero bit
Power loss Flag bit
Time overflow Flag bit
General purpose bit
Function
(5) MSR (Memory Select Register) : R4
(6) PORT A : R5
PA3~PA0, I/O Register
(7) PORT B : R6
PB7~PB0, I/O Register
(8) TMR (Time Mode Register)
Bit
Symbol
Prescaler Value
Function
RTCC rate
WDT rate
0 0 0
1:2
1:1
0 0 1
1:4
1:2
0 1 0
1:8
1:4
0 1 1
1 : 16
1:8
1 0 0
1 : 32
1 : 16
1 0 1
1 : 64
1 : 32
1 1 0
1 : 128
1 : 64
1 1 1
1 : 256
1 : 128
Prescaler assignment bit :
0
—
RTCC
1
—
Watchdog Timer
RTCC signal Edge :
0
—
Increment on low-to-high transition on RTCC pin
1
—
Increment on high-to-low transition on RTCC pin
RTCC signal set :
0
—
Internal instruction cycle clock
1
—
Transition on RTCC pin
2—0
PS2—0
3
PSC
4
TCE
5
TCS
This specification are subject to be changed without notice. Any latest information
please preview http;//www.mdtic.com.tw
P. 3
2006/4
VER1.1
MDT2005(JG)
(9) CPIO A, CPIO B (Control Port I/O Mode Register)
The CPIO register is “write-only”
＝“0”,
I/O pin in output mode;
＝“1”,
I/O pin in input mode.
(10) EPROM Option by writer programming :
Oscillator Type
RC
Oscillator
Oscillator Start-up Time
150
µs,20ms,40ms,80ms
20 ms,40ms,80ms
20ms,40 ms,80ms
40 ms,80 ms
HFXT Oscillator
XTAL Oscillator
LFXT Oscillator
Watchdog Timer control
Watchdog timer disable all the time
Watchdog timer enable all the time
Power Edge Detect
PED Disable
PED Enable
Security bit
Security weak Disable
Security Disable
Security Enable
The default EPROM security is weak disable. Once the IC was set in enable or disable, it’s
forbidden to set in disable or enable again.
(B) Program Memory
Address
000-1FF
1FF
Description
Program memory for MDT2005
The starting address of the power on, external
reset or WDT for MDT2005
This specification are subject to be changed without notice. Any latest information
please preview http;//www.mdtic.com.tw
P. 4
2006/4
VER1.1
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