CML Microcircuits
COMMUNICA
TION SEMICONDUCTORS
CMX7143
Multi-Mode Wireless
Data Modem
Provisional Issue
D/7143_FI2.0/10 May 2013
DATASHEET
7143FI-2.x 4FSK Packet Data Modem
Features
Multiple Modulation Types
o
7143 FI-1.0: GMSK/GFSK Modulation
o
7143 FI-2.0: 4FSK Modulation -
Over-air
compatibility with CMX969 for RD-LAP Tx/Rx
Flexible Bit Rates
Raw Mode, Data Pump, Carrier Sense
Auxiliary System Clock Outputs
Tx Outputs for 2-point or I/Q Modulation
Available in 48-pin LQFP and VQFN Packages
Low-power 3.3V Operation
Flexible Powersave Modes
Formatted or Raw Data Modes
Soft Decision Data Bits
o
7143 FI-3.0: FFSK/MSK Modulation
Automatic Frame Sync Detection
Automatic Preamble, Frame Sync Insertion
2 x Auxiliary ADCs and 4 x Auxiliary DACs
3 x Analogue Inputs (RSSI or Discriminator)
C-BUS Serial Interface to Host µController
CMX7143
System Clk
C-BUS
registers
Status
System
Mode/Aux
Host µC
C-BUS
Clock
Synthesizers
2 aux ADCs
3 aux DACs
1 aux/RAM DAC
Tx Trigger Input
GPIO
Data Buffer
Tx Sequence
Control
MOD1 gain
MOD2 gain
Rx
RSSI
Data
Modem
Tx
Rx
CS
Modulator
RF
Discriminator
Config (in
Idle)
Configuration
Parameters
1
Brief Description
Designed for use in wireless data modems, the CMX7143 with 7143FI-2.x is a half-duplex modem with
carrier sense and automatic control of transmit hardware, including a RAMDAC for PA ramping. Carrier
sense provides a listen before talk capability, automatically reverting to receive if activity on channel is
detected. In receive, automatic frame sync detection provides acquisition of the received signal with
minimal host intervention. Two different frame sync patterns may be searched for concurrently, with little
need for preamble.
Continued...
2013 CML Microsystems Plc
CMX7143 FI-2: 4FSK Multi-Mode Wireless Data Modem
CMX7143
Other features include two Auxiliary ADC channels with four selectable inputs and up to four auxiliary DAC
outputs (with an optional RAMDAC on the first DAC output, to facilitate transmitter power ramping).
Coded mode supports block types compatible with the CMX919 and CMX969 (RD-LAP) modems.
The device has flexible powersaving modes and is available in both LQFP and VQFN packages.
The device utilises CML’s proprietary
FirmASIC
component technology. On-chip sub-systems are
configured by a Function Image™: this is a data file that is uploaded during device initialisation and defines
the device's function and feature set. The Function Image™ can be loaded automatically from an external
EEPROM or from a host µController over the built-in C-BUS serial interface. The device's functions and
features can be enhanced by subsequent Function Image™ releases, facilitating in-the-field upgrades.
This document refers specifically to the features provided by Function Image™ 7143FI-2.x. Separate
Function Images™ are available which support GFSK/GMSK and FFSK/MSK modulation.
This Datasheet is the first part of a two-part document comprising Datasheet and User Manual: the User
Manual can be obtained by registering your interest in this product with your local CML representative.
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CMX7143
CONTENTS
Section
1
2
3
4
5
6
7
Page
Brief Description ...................................................................................................................... 1
Block Diagram .......................................................................................................................... 7
Signal List................................................................................................................................. 8
External Components............................................................................................................ 10
PCB Layout Guidelines and Power Supply Decoupling .................................................... 12
General Description............................................................................................................... 13
6.1
CMX7143 Features..................................................................................................... 13
Detailed Descriptions ............................................................................................................ 14
7.1
Xtal Frequency............................................................................................................ 14
7.2
Host Interface ............................................................................................................. 14
7.2.1 C-BUS Operation ................................................................................................. 14
7.3
Function Image™ Loading.......................................................................................... 16
7.3.1 FI Loading from Host Controller ........................................................................... 16
7.3.2 FI Loading from Serial Memory ............................................................................ 18
7.4
Device Control ............................................................................................................ 19
7.4.1 Normal Operation Overview ................................................................................. 19
7.4.2 Device Configuration (Using the Programming register) ..................................... 20
7.4.3 Device Configuration (Using dedicated registers) ................................................ 20
7.4.4 Interrupt Operation ............................................................................................... 20
7.4.5 Signal Routing ...................................................................................................... 21
7.4.6 Tx Mode ............................................................................................................... 21
7.4.7 Rx Mode ............................................................................................................... 22
7.4.8 Carrier Sense Mode ............................................................................................. 25
7.4.9 The Transmit Sequence ....................................................................................... 27
7.4.10 Other Modem Modes ........................................................................................... 27
7.4.11 Data Transfer ....................................................................................................... 28
7.4.12 Raw Data Transfer ............................................................................................... 29
7.4.13 Formatted Data Transfer ...................................................................................... 29
7.4.14 Pre-loading Transmit Data ................................................................................... 29
7.4.15 Auxiliary Clock Rates ........................................................................................... 29
7.4.16 Auxiliary Data ....................................................................................................... 30
7.4.17 GPIO Pin Operation ............................................................................................. 30
7.4.18 Auxiliary ADC Operation ...................................................................................... 30
7.4.19 Auxiliary DAC/RAMDAC Operation ...................................................................... 31
7.5
Digital System Clock Generators ................................................................................ 32
7.5.1 System Clock Operation ...................................................................................... 33
7.5.2 Main Clock Operation........................................................................................... 33
7.6
Signal Level Optimisation ........................................................................................... 33
7.6.1 Transmit Path Levels ........................................................................................... 33
7.6.2 Receive Path Levels............................................................................................. 33
7.7
C-BUS Register Summary.......................................................................................... 34
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8
7143FI-2.x Features ............................................................................................................... 35
8.1
Modulation .................................................................................................................. 35
8.2
Radio Interface ........................................................................................................... 36
8.3
Formatted Data ........................................................................................................... 37
8.4
Cyclic Redundancy Codes .......................................................................................... 40
8.5
Transmit Performance ................................................................................................ 41
8.6
Receive Performance ................................................................................................. 47
Performance Specification ................................................................................................... 48
9.1
Electrical Performance ............................................................................................... 48
9.1.1 Absolute Maximum Ratings ................................................................................. 48
9.1.2 Operating Limits ................................................................................................... 48
9.1.3 Operating Characteristics..................................................................................... 49
9.1.4 Parametric Performance ...................................................................................... 54
9.2
C-BUS Timing ............................................................................................................. 55
9.3
Packaging ................................................................................................................... 56
Page
9
Table
Table 1 BOOTEN Pin States ......................................................................................................... 16
Table 2 C-BUS Data Registers ..................................................................................................... 28
Table 3 C-BUS Registers .............................................................................................................. 34
Figure
Page
Figure 1 Block Diagram ................................................................................................................... 7
Figure 2 CMX7143 Recommended External Components ........................................................... 10
Figure 3 CMX7143 Power Supply and De-coupling ...................................................................... 12
Figure 4 C-BUS Transactions ....................................................................................................... 15
Figure 5 FI Loading from Host ...................................................................................................... 17
Figure 6 FI Loading from Serial Memory....................................................................................... 18
Figure 7 Host Tx Data Flow (No Tx sequence/Carrier sense) ...................................................... 22
Figure 8 Host Rx Data Flow (Use Trans=0) .................................................................................. 23
Figure 9 Host Rx Data Flow (Flow controlled data with UseTrans=1) .......................................... 24
Figure 10 Carrier Sense ................................................................................................................ 26
Figure 11 Transmit Sequence ....................................................................................................... 27
Figure 12 Digital Clock Generation Schemes ............................................................................... 32
Figure 13 4FSK PRBS Waveform ................................................................................................. 35
Figure 14 Outline Radio Design .................................................................................................... 36
Figure 15 Formatted Data Over Air Signal Format ....................................................................... 37
Figure 16 Some Alternative Frame Structures .............................................................................. 38
Figure 17 RD-LAP Over Air Signal Format ................................................................................... 39
Figure 18 Tx Spectrum and Modulation Measurement Configuration .......................................... 41
Figure 19 Tx Modulation Spectra (4FSK), 19200bps, 2-point modulation .................................... 42
Figure 20 Tx Modulation Spectra (4FSK), 9600bps (4800 symb/s), 2point modulation................ 43
Figure 21 Tx Modulation Spectra (4FSK), 4800bps – 2-point modulation .................................... 44
Figure 22 Tx Spectrum and Modulation Measurement Configuration for I/Q Operation............... 44
Figure 23 Tx Modulation Spectra (4FSK), 9600bps (4800 symb/s), I/Q modulation .................... 45
Figure 24 Tx Modulation Spectra (4FSK), 19200bps (9600 symb/s), I/Q modulation .................. 46
Figure 25 C-BUS Timing ............................................................................................................... 55
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Figure 26 Mechanical Outline of 48-pin VQFN (Q3) ..................................................................... 56
Figure 27 Mechanical Outline of 48-pin LQFP (L4) ....................................................................... 56
It is always recommended that you check for the latest product datasheet version from the CML website:
[www.cmlmicro.com].
History
Version
10
9
8
Changes
Added RD-LAP channel coding block types in FI-2.x.
Clarification of BOOTEN options by Table 1 and Table 4.
Correction of error in Figure 6.
Clarification of P4.x program block nomenclature and minor typographical
errors. Clarification of maximum bit/byte counter value in raw mode (TxData 0
and RxData 0). Definition of the action of any unused bits added. Default pre-
amble length in P0.8 corrected to 18 symbols.
Additional information about CRC2 Reset, Insert Preamble, insert FS1 and
insert FS2 features added in 7143FI-2.1.2.0.
Clarification of additional delay required when preloading data in Tx Idle or CS
Idle modes, in section 7.4.14, and additional delays for all consecutive C-BUS
writes.
Changes to Pin names, Register and Bit names for consistency with other FIs.
(Functionality is unchanged, but drawings, tables and text descriptions updated).
Addition of a “Last tail” status bit in Tx for 7143FI-2.1.1.0. Description added.
Table in section 11.1 replaced by a hyperlinked register table.
Descriptions of the b15..12 allocation in section 11.2.4 corrected.
Definition of maximum signal levels clarified.
Details of Fine output attenuation in Program Blocks P4.9 and P4.10 added.
FI loading procedure, P3.x tables and Reset mechanisms clarified.
Style of EDS changed to conform to latest guidelines, logos, etc. also updated.
Document is now "Provisional Issue".
Changes to Program Block P4.1 specification to allow for selection of Tx
RRC+Sinc and an Rx RRC+Inverse Sinc filter OR RRC for both Tx and Rx.
Changes to Program Block P4.1 specification to allow for selection of soft bit
outputs in raw mode.
Changes to the description of RxData registers and RxControl register to define
soft output operation.
Error in power up bit specification corrected (Power Down Control register).
Added explanation of RSSI and inverted P4.7 and P4.8 in Program Blocks.
Minor typographical corrections.
Correction in rates that the host should read/write Aux Data Control registers.
Correction to time units used to specify Carrier Sense/Tx Sequence.
Added reference to "CMX7143 Modem Performance" App. Note.
Add operating current in ‘DC Parameters’.
Remove DC blocking capacitors from signal inputs (figure 2).
Editorial formatting of AV
DD
in P1.2 default values and other minor typographical
corrections.
Clarification of which bits are used in raw and formatted modes in register $C3.
Correction of description of b5 in $C6 concerning RxData0 ($B8) and TxData0
($B5).
Section 11.1, $C6, b1 corrected to ‘X’.
Date
15.5.13
26.7.11
01.12.09
7
06.10.09
6
31.07.09
5
04.02.09
4
17.06.08
3
13.05.08
2013 CML Microsystems Plc
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