The CYK512K16SCCA is a high-performance CMOS pseudo
static RAM (PSRAM) organized as 512K words by 16 bits that
supports an asynchronous memory interface. This device
features advanced circuit design to provide ultra-low active
current. This is ideal for providing More Battery Life (MoBL)
in portable applications such as cellular telephones. The
device can be put into standby mode reducing power
consumption dramatically when deselected (CE
1
LOW, CE
2
HIGH or both BHE and BLE are HIGH). The input/output pins
(I/O
0
through I/O
15
) are placed in a high-impedance state
when: deselected (CE
1
HIGH, CE
2
LOW), OE is deasserted
HIGH, or during a write operation (Chip Enabled and Write
Enable WE LOW). Reading from the device is accomplished
by asserting the Chip Enables (CE
1
LOW and CE
2
HIGH) and
Output Enable (OE) LOW while forcing the Write Enable (WE)
HIGH. If Byte Low Enable (BLE) is LOW, then data from the
memory location specified by the address pins will appear on
I/O
0
to I/O
7
. If Byte High Enable (BHE) is LOW, then data from
memory will appear on I/O
8
to I/O
15
. See the Truth Table for a
complete description of read and write modes.
Logic Block Diagram
DATA IN DRIVERS
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
ROW DECODER
512K x 16
RAM Array
SENSE AMPS
I/O
0
–I/O
7
I/O
8
–I/O
15
COLUMN DECODER
BHE
WE
OE
BLE
BHE
BLE
CE
2
CE
1
CE
2
CE
1
Note:
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
A
11
A
12
A
13
A
14
A
15
A
16
A
17
A
18
Pow
-
er Down
Circuit
Cypress Semiconductor Corporation
Document #: 38-05425 Rev. *C
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Revised May 13, 2004
CYK512K16SCCA
MoBL
Pin Configuration
[2, 3, 4]
48-Ball FBGA
Top View
4
2
3
1
BLE
I/O
8
I/O
9
V
SS
V
CC
I/O
14
I/O
15
A
18
5
A
2
CE
1
I/O
1
I/O
3
I/O
4
I/O
5
WE
A
11
6
CE
2
I/O
0
I/O
2
V
CC
V
SS
I/O
6
I/O
7
NC
A
B
C
D
E
F
G
H
OE
BHE
I/O
10
I/O
11
A
0
A
3
A
5
A
17
A
1
A
4
A
6
A
7
A
16
A
15
A
13
A
10
I/O
12
DNU
I/O
13
NC
A
8
A
14
A
12
A
9
Product Portfolio
[5]
Power Dissipation
V
CC
Range
(V)
Product
CYK512K16SCCA
Min.
2.7
Typ.
3.0
Max.
3.3
Operating, I
CC
(mA)
Speed
(ns)
55
70
f = 1 MHz
Typ.
[5]
2
Max.
5
f = f
MAX
Typ.
[5]
11
Max.
22
17
Standby, I
SB2
(µA)
Typ.
[5]
55
Max.
100
Notes:
2. DNU pins are to be left floating or tied to V
SS
.
3. Ball G2, H6 are the address expansion pins for the 16-Mbit and 32-Mbit densities respectively.
4. NC “no connect”—not connected internally to the die.
5. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC
(typ) and T
A
= 25°C.
Document #: 38-05425 Rev. *C
Page 2 of 10
CYK512K16SCCA
MoBL
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied .............................................. –40°C to +85°C
Supply Voltage to Ground Potential ................
−0.4V
to 4.6V
DC Voltage Applied to Outputs
in High-Z State
[6, 7, 8]
.......................................
−0.4V
to 3.7V
Range
Industrial
DC Input Voltage
[6, 7, 8]
....................................−0.4V to 3.7V
Output Current into Outputs (LOW) ............................ 20 mA
Static Discharge Voltage ......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current .................................................... > 200 mA
Operating Range
Ambient
Temperature (T
A
)
−25°C
to +85°C
V
CC
2.7V to 3.3V
DC Electrical Characteristics
(Over the Operating Range)
[5, 6, 7, 8]
CYK512K16SCCA-55
Parameter
Vcc
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
Description
Supply Voltage
Output HIGH Voltage I
OH
=
−0.1
mA
Output LOW Voltage I
OL
= 0.1 mA
Input HIGH Voltage
Input LOW Voltage
Input Leakage
Current
Output Leakage
Current
V
CC
Operating
Supply Current
F=0
GND < V
IN
< V
CC
GND < V
OUT
< V
CC
, Output
Disabled
f = f
MAX
= 1/t
RC
V
CC
= 3.3V,
I
OUT
= 0 mA,
f = 1 MHz
CMOS level
0.8 *
V
CC
−0.4
−1
−1
11
2
100
Test Conditions
Min.
2.7
V
CC
–
0.4
0.4
V
CC
+
0.4
0.4
+1
+1
22
5
400
0.8 *
V
CC
−0.4
−1
−1
11
2
100
Typ.
[5]
3.0
Max.
3.3
CYK512K16SCCA-70
Min.
2.7
V
CC
–
0.4
0.4
V
CC
+
0.4
0.4
+1
+1
17
5
400
µA
Typ.
[5]
Max.
3.3
Unit
V
V
V
V
V
µA
µA
mA
I
SB1
Automatic CE
1
CE > V
CC
−
0.2V, CE
2
< 0.2V
Power-down Current V
IN
> V
CC
−
0.2V, V
IN
< 0.2V,
f = f
MAX
(Address and Data Only),
—CMOS Inputs
f = 0 (OE, WE, BHE and BLE)
Automatic CE
1
CE > V
CC
−
0.2V, CE
2
< 0.2V
Power-down Current V
IN
> V
CC
−
0.2V or V
IN
< 0.2V,
f = 0, V
CC
=3.3V
—CMOS Inputs
I
SB2
55
100
55
100
µA
Capacitance
[9]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz
V
CC
= V
CC(typ)
Max.
8
8
Unit
pF
pF
Thermal Resistance
[9]
Parameter
θ
JA
θ
JC
Description
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Test Conditions
Test conditions follow standard test methods
and procedures for measuring thermal
impedance, per EIA / JESD51.
FBGA
55
17
Unit
°C/W
°C/W
Notes:
6. V
IH(MAX)
= V
CC
+ 0.5V for pulse durations less than 20 ns.
7. V
IL(MIN)
= –0.5V for pulse durations less than 20 ns.
8. Overshoot and undershoot specifications are characterized and are not 100% tested.
9. Tested initially and after design or process changes that may affect these parameters.
Document #: 38-05425 Rev. *C
Page 3 of 10
CYK512K16SCCA
MoBL
AC Test Loads and Waveforms
V
CC
OUTPUT
R1
V
CC
GND
30 pF
INCLUDING
JIG AND
SCOPE
Parameters
R1
R2
R
TH
V
TH
R2
10%
ALL INPUT PULSES
90%
90%
10%
Fall Time = 1 V/ns
Rise Time = 1 V/ns
Equivalent to: THEVENIN EQUIVALENT
RTH
OUTPUT
VTH
3.0V V
CC
22000
22000
11000
1.50
Unit
Ω
Ω
Ω
V
Switching Characteristics
(Over the Operating Range)
[10, 11, 12, 13, 14]
CYK512K16SCCA-55
Parameter
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
DBE
t
LZBE
t
HZBE
t
SK[14]
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE
1
LOW and CE
2
HIGH to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
[11, 12]
OE HIGH to High Z
[11, 12]
CE
1
LOW and CE
2
HIGH to Low Z
[11, 12]
CE
1
HIGH and CE
2
LOW to High Z
[11, 12]
BLE/BHE LOW to Data Valid
BLE/BHE LOW to Low Z
[11, 12]
BLE/BHE HIGH to High-Z
[11, 12]
Address Skew
5
10
0
5
25
55
5
25
10
5
25
5
25
70
5
55
25
5
25
55
[14]
55
5
70
35
70
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
CYK512K16SCCA-70
Min.
Max.
Unit
Notes:
10. Test conditions assume signal transition time of 1V/ns or higher, timing reference levels of V
CC(typ)
/2, input pulse levels of 0V to V
CC(typ),
and output loading of
the specified I
OL
/I
OH
and 30-pF load capacitance
11. t
HZOE
, t
HZCE
, t
HZBE
and t
HZWE
transitions are measured when the outputs enter a high-impedance state.
12. High-Z and Low-Z parameters are characterized and are not 100% tested.
13. The internal write time of the memory is defined by the overlap of WE, CE
1
= V
IL
, CE
2
= V
IH
, BHE and/or BLE =V
IL
. All signals must be ACTIVE to initiate a write
and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that
terminates write.
14. To achieve 55-ns performance, the read access should be CE controlled. In this case t
ACE
is the critical parameter and t
SK
is satisfied when the addresses are
stable prior to chip enable going active. For the 70-ns cycle, the addresses must be stable within 10 ns after the start of the read cycle.
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