PRELIMINARY
CY7C1395
CY7C1395V25
2M x 36 PBSRAM with NoBL-Burst™ Architecture
Features
• Pin-compatible to ZBT™ and NoBL™ devices
• Supports up to166-MHz bus operations with zero wait
states
— Data is transferred on every clock
• Internally self-timed output buffer control to eliminate
the need to use asynchronous OE
• Fully registered (inputs and outputs) for pipelined
operation
• Byte Write capability
• Common I/O architecture
• Single 2.5V or 3.3V power supply
• Fast clock-to-output times
— 3.5 ns (for 166-MHz device)
— 4.2 ns (for 133-MHz device)
•
•
•
•
•
— 5.0 ns (for 100-MHz device)
Clock Enable (CEN) pin to suspend operation
Synchronous self-timed writes
Available in 100 TQFP package
119 BGA package is offered by opportunity basis
(Check with Cypress sales and marketing)
Burst Capability—linear or interleaved burst order
Functional Description
The CY7C1395V25 and CY7C1395 are 2.5V and 3.3V
2M × 36 synchronous pipelined burst SRAMs designed
specifically to support unlimited true back-to-back Read/Write
operations without the insertion of wait states. The
CY7C1395V25 operates with a 2.5V power supply and the
CY7C1395 operates with a 3.3V power supply. Both are
equipped with the advanced No Bus Latency-Burst™
(NoBL-Burst™) logic required to enable consecutive
Read/Write operations with data being transferred on every
clock cycle. This feature dramatically improves the throughput
of data through the SRAM, especially in systems that require
frequent Write/Read transitions.The CY7C1395V25 and
CY7C1395 are pin-compatible with ZBT and NoBL devices.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN) signal,
which when deasserted suspends operation and extends the
previous clock cycle. Maximum access delay from the clock
rise is 3.5 ns (166-MHz device).
Write operations are controlled by the Byte Write Selects and
a Write Enable (WE) input. All writes are conducted with
on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
D
Data-In REG.
Q
Logic Block Diagram
CLK
CE
A
[20:0]
CEN
CE
1
CE2
CE3
WE
BWS
[a:d]
Mode
CONTROL
and WRITE
LOGIC
2MX36
MEMORY
ARRAY
OUTOUT
REGISTERS
and LOGIC
ADV/LD
DQ
[31:0]
DP
[3:0]
OE
Selection Guide
-166
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Shaded area contains advanced information.
-133
4.2
200
20
-100
5.0
175
20
Unit
ns
mA
mA
3.5
220
20
Cypress Semiconductor Corporation
Document #: 38-05183 Rev. *A
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Revised February 19, 2003
PRELIMINARY
Pin Configurations
100-pin TQFP Package
A
A
CE
1
CE
2
BWSd
BWSc
BWSb
BWSa
CE
3
V
DD
V
SS
CLK
WE
CEN
OE
ADV/LD
A
A
A
A
CY7C1395
CY7C1395V25
DPc
DQc
DQc
V
DDQ
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
V
SS
DQc
DQc
DQc
DQc
V
SS
V
DDQ
DQc
DQc
Vdd
V
DD
V
DD(1)
V
SS
DQd
DQd
V
DDQ
V
SS
DQd
DQd
DQd
DQd
V
SS
V
DDQ
DQd
DQd
DPd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1395
(2M x 36)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DPb
DQb
DQb
V
DDQ
V
SS
DQb
DQb
DQb
DQb
V
SS
V
DDQ
DQb
DQb
V
SS
V
DD(1)
V
DD
Vss
DQa
DQa
V
DDQ
V
SS
DQa
DQa
DQa
DQa
V
SS
V
DDQ
DQa
DQa
DPa
MODE
A
A
A
A
A
1
A
0
DNU
DNU
V
SS
V
DD
Document #: 38-05183 Rev. *A
A
A
A
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Page 2 of 23
PRELIMINARY
Pin Configurations
(continued)
119-ball Bump BGA
CY7C1395 (2M × 36) – 7 × 17 BGA
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DPc
DQc
V
DDQ
DQc
DQc
V
DDQ
DQd
DQb
V
DDQ
DQd
DPd
NC
NC
V
DDQ
CY7C1395
CY7C1395V25
2
A
CE
2
A
DQc
DQc
DQc
DQb
DQc
V
DD
DQd
DQd
DQd
DQd
DQd
A
A
TMS
3
A
A
A
V
SS
V
SS
V
SS
BWSc
V
SS
NC
V
SS
BWSd
V
SS
V
SS
V
SS
MODE
A
TDI
4
A
ADV/LD
V
DD
NC
CE
1
OE
A
WE
V
DD
CLK
NC
CEN
A1
A0
V
DD
A
TCK
5
A
A
A
V
SS
V
SS
V
SS
BWSb
V
SS
NC
V
SS
BWSa
V
SS
V
SS
V
SS
6
A
CE
3
A
DQb
DQb
DQb
DQb
DQb
V
DD
DQa
DQa
DQa
DQa
DQa
A
A
NC
7
V
DDQ
NC
NC
DPb
DQb
V
DDQ
DQb
DQb
V
DDQ
DQa
DQa
V
DDQ
DQa
DPa
NC
V
SS
V
DDQ
Vdd
A
TDO
Pin Definitions (CY7C1395)
Name
A0
A1
A(2:20)
BWSa
BWSb
BWSc
BWSd
WE
ADV/LD
I/O Type
Input-
Synchronous
Input-
Synchronous
Description
Address inputs used to select one of the memory locations in the array.
Sampled at the rising
edge of the CLK.
Byte Write Select Inputs, active LOW.
Enables or masks write data during active write cycles.
Byte Writes must be valid two cycles before the write data. Sampled on the rising edge of CLK.
BWSa controls DQa and DPa, BWSb controls DQb and DPb, BWSc controls DQc and DPc, BWSd
controls DQd and DPd.
Write Enable Input, active LOW.
Sampled on the rising edge of CLK if CEN is active LOW. This
signal must be asserted LOW to initiate a write sequence.
Advance/Load Input used to advance the on-chip address counter or load a new address.
When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a
new address can be loaded into the device for an access.
Clock Input.
Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK
is only recognized if CEN is active LOW.
Chip Enable 1 Input, active LOW.
Sampled on the rising edge of CLK. Used in conjunction with
CE
2
and CE
3
to select/deselect the device.
Chip Enable 2 Input, active HIGH.
Sampled on the rising edge of CLK. Used in conjunction with
CE
1
and CE
3
to select/deselect the device.
Chip Enable 3 Input, active LOW.
Sampled on the rising edge of CLK. Used in conjunction with
CE
1
and CE
2
to select/deselect the device.
Input-
Synchronous
Input-
Synchronous
Input-
Clock
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
CLK
CE
1
CE
2
CE
3
OE
Input-
Output Enable, active LOW.
Combined with the synchronous logic block inside the device to
Asynchronous control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs.
When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked once
a write operation has been initiated, during the first clock when emerging from a deselected state
and when the device has been deselected.
Document #: 38-05183 Rev. *A
Page 3 of 23
PRELIMINARY
Pin Definitions (CY7C1395)
(continued)
Name
CEN
I/O Type
Input-
Synchronous
I/O-
Synchronous
Description
CY7C1395
CY7C1395V25
Clock Enable Input, active LOW.
When asserted LOW the clock signal is recognized by the
SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not
deselect the device, CEN can be used to extend the previous cycle when required.
Bidirectional Data I/O lines.
As inputs, they feed into an on-chip data register that is triggered by
the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified
by A
[17:0]
during the initiation of the burst. The direction of the pins is controlled by OE and the
internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH,
DQa–DQd are placed in a three-state condition. The outputs are automatically three-stated once
a write operation has been initiated, and during the first clock when emerging from a deselected
state, and when the device is deselected, regardless of the state of OE.
Bidirectional Data Parity I/O lines.
Functionally, these signals are identical to DQ
[31:0]
. During
write sequences, DPa is controlled by BWSa, DPb is controlled by BWSb, DPc is controlled by
BWSc, and DPd is controlled by BWSd.
DQa
DQb
DQc
DQd
DPa
DPb
DPc
DPd
MODE
I/O-
Synchronous
Input Strap Pin
Mode Input.
Selects the burst order of the device. Tied HIGH selects the interleaved burst order.
Pulled LOW selects the linear burst order. MODE should not change states during operation. When
left floating MODE will default HIGH, to an interleaved burst order.
Power Supply
Power supply inputs to the core of the device.
I/O Power
Supply
Ground
Input Static
–
–
JTAG output-
Synchronous
JTAG input-
Synchronous
JTAG input-
Synchronous
JTAG input-
Clock
–
–
Power supply for the I/O circuitry.
Ground for the device.
Should be connected to ground of the system.
These pins have to be tied to a voltage level > Vih.
They need not be tied to Vdd.
No connect.
This pin is reserved ZZ function and is not connected to the die. May be tied high.
Do Not Use pins.
These pins should be left floating or tied to V
SS
.
Serial data-out to the JTAG circuit.
Delivers data on the negative edge of TCK.
Serial data-in to the JTAG circuit.
Sampled on the rising edge of TCK.
This pin controls the Test Access Port state machine.
Sampled on the rising edge of TCK.
Clock input to the JTAG circuitry.
No connects.
No connect, to be determined whether connected to V
DD
or V
SS
. These pins will not affect the
functionality of the product. These pins can be left not connected to the internal die.
V
DD
V
DDQ
V
SS
V
dd(1)
NC
DNU
TDO
TDI
TMS
TCK
NC
NC(1)
Document #: 38-05183 Rev. *A
Page 4 of 23
PRELIMINARY
Introduction
Functional Overview
The CY7C1395V25 and CY7C1395 are synchronous
pipelined NoBL-Burst SRAMs designed specifically to
eliminate wait states during Write/Read transitions. All
synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock signal is qualified with
the Clock Enable input signal (CEN). If CEN is HIGH, the clock
signal is not recognized and all internal states are maintained.
All synchronous operations are qualified with CEN. All data
outputs pass through output registers controlled by the rising
edge of the clock. Maximum access delay from the clock rise
(t
CO
) is 3.5 ns (166-MHz device).
Accesses can be initiated by asserting all three Chip Enables
(CE
1
, CE
2
, CE
3
) active at the rising edge of the clock. If Clock
Enable (CEN) is active LOW and ADV/LD is asserted LOW,
the address presented to the device will be latched. The
access can either be a read or write operation, depending on
the status of the Write Enable (WE). BWS
[x]
can be used to
conduct byte write operations.
Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self-timed write
circuitry.
Three synchronous Chip Enables (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) simplify depth expansion.
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD should be driven LOW once the device has been
deselected in order to load a new address for the next
operation.
Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE
1
, CE
2,
and CE
3
are ALL asserted active, (3) the Write Enable input
signal WE is deasserted HIGH, and (4) ADV/LD is asserted
LOW. The address presented to the address inputs is latched
into the Address Register and presented to the memory core
and control logic. The control logic determines that a read
access is in progress and allows the requested data to
propagate to the input of the output register. At the rising edge
of the next clock the requested data is allowed to propagate
through the output register and onto the data bus within 3.5 ns
(166-MHz device), provided OE is active LOW. After the first
clock of the read access the output buffers are controlled by
OE and the internal control logic. OE must be driven LOW in
order for the device to drive out the requested data.
The NoBL-Burst architecture supports burst accesses
only. Each Read access must be allowed to complete a
burst sequence of four word. Each burst of four words is
non-interruptible.
Therefore, ADV/LD must be driven HIGH
in order to increment the burst counter, throughout the entire
burst sequence. Each Read access must be allowed to
complete prior to the initiation of a new access (Read, Write or
Deselect). Therefore, the input signals CE
1
, CE
2,
CE
3
, WE,
and BWSx will be ignored for the three clock rises (CEN active
LOW) after the initiation of the access.
The sequence of the burst counter is determined by the MODE
input signal. A LOW input on MODE selects a linear burst
mode, a HIGH selects an interleaved burst sequence. Both
burst counters use A0 and A1 in the burst sequence (see burst
sequence tables for details). Both burst counters will
CY7C1395
CY7C1395V25
wrap-around when incremented sufficiently. If incremented
sufficiently to wrap-around, the sequence of four read
accesses must be allowed to be complete as if a new access
was initiated. ADV/LD must be asserted LOW in order to load
a new address into the SRAM. Consecutive read operations is
supported such that data is latched out of the device on every
clock rise. See timing diagrams for further details.
The type of access (Read, Write or Deselect) is established at
the initiation of the burst. Therefore CE
1
, CE
2,
CE
3
, WE and
BWSx are ignored during the burst portion of a Read access.
Deselecting the device is also pipelined (double cycle
deselect). Therefore, when the SRAM is deselected at clock
rise, its output will three-state following the next clock rise.
Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE
1
, CE
2
,
and CE
3
are ALL asserted active, and (3) the write signal WE
is asserted LOW. The address presented to the SRAM is
loaded into the Address Register and the byte write signals are
latched into the Control Logic block.
On the subsequent clock rise the data lines are automatically
three-stated regardless of the state of the OE input signal. This
allows the external logic to present the data on DQ and DP
inputs. On the next clock rise the data presented to DQ and
DP inputs (or a subset for byte write operations, see Write
Cycle Description Table for details) is latched into the device.
The NoBL-Burst architecture supports burst accesses
only. Each Write access must be allowed to complete a
burst sequence of four words. Each burst of four is
non-interruptible.
Therefore, the input signals CE
1
, CE
2,
CE
3
and WE will be ignored for the three clock rises (CEN active
LOW) after the initiation of the access. Consecutive Write
operation is supported such that data is latched into the device
on every clock rise.
The data written during the Write operation is controlled by
BWS
x
signals. Asserting the appropriate Byte Write Select
(BWS
x
) input will selectively write to only the desired bytes.
The BWS
x
inputs are sampled two clocks prior to the actual
data being latched into the device (see timing diagrams for
details). Bytes not selected during a byte write operation will
remain unaltered.
Deasserting all Byte Write Select inputs inactive HIGH will
create a NOP/DUMMY Write. This is a Write cycle where no
data is written into the device. Parts or all of a write sequence
can consist of NOP/DUMMY Writes. The address counter is
incremented during NOP/DUMMY Writes.
Deselecting the device is also pipelined (double cycle
deselect). Therefore, when the SRAM is deselected at clock
rise, the Write operations in progress are allowed to complete.
The type of access (Read, Write or Deselect) is established at
the initiation of the burst. Therefore CE
1
, CE
2,
CE
3
and WE are
ignored during the burst portion of a Write access.
A Synchronous self-timed write mechanism has been
provided to simplify the write operations. Byte write capability
has been included in order to greatly simplify
Read/Modify/Write sequences, which can be reduced to
simple byte write operations.
ADV/LD must be driven LOW in order to load the initial
address, as described above. The sequence of the burst
Document #: 38-05183 Rev. *A
Page 5 of 23
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