PRELIMINARY
CY7C1370A
CY7C1372A
512Kx36/1Mx18 Pipelined SRAM with NoBL™ Architecture
Features
• Zero Bus Latency, no dead cycles between write and
read cycles
• Fast clock speed: 167, 150, 133, and 100 MHz
• Fast access time: 3.4, 3.8, 4.2, 5.0 ns
• Internally synchronized registered outputs eliminate
the need to control OE
• Single 3.3V –5% and +5% power supply V
DD
• Separate V
DDQ
for 3.3V or 2.5V I/O
• Single WE (READ/WRITE) control pin
• Positive clock-edge triggered, address, data, and con-
trol signal registers for fully pipelined applications
• Interleaved or linear 4-word burst capability
• Individual byte write (BWSa - BWSd) control (may be
tied LOW)
• CEN pin to enable clock and suspend operations
• Three chip enables for simple depth expansion (TQFP
Package Only)
• JTAG boundary scan (BGA Package Only)
• Available in 119-ball bump BGA and 100-pin TQFP pack-
ages
All synchronous inputs are gated by registers controlled by a
positive-edge-triggered Clock Input (CLK). The synchronous
inputs include all addresses, all data inputs, depth-expansion
Chip Enables (CE
1
, CE
2
, and CE
3
), cycle start input (ADV/LD),
Clock Enable (CEN), Byte Write Enables (BWSa, BWSb,
BWSc, and BWSd), and Read-Write Control (WE). BWSc and
BWSd apply to CY7C1370A only.
Address and control signals are applied to the SRAM during
one clock cycle, and two cycles later, its associated data oc-
curs, either read or write.
A Clock Enable (CEN) pin allows operation of the
CY7C1370A/CY7C1372A to be suspended as long as neces-
sary. All synchronous inputs are ignored when CEN is HIGH
and the internal device registers will hold their previous values.
There are three chip enable pins (CE
1
, CE
2
, CE
3
) that allow
the user to deselect the device when desired. If any one of
these three are not active when ADV/LD is LOW, no new mem-
ory operation can be initiated and any burst cycle in progress
is stopped. However, any pending data transfers (read or write)
will be completed. The data bus will be in high-impedance
state two cycles after the chip is deselected or a write cycle is
initiated.
The CY7C1370A and CY7C1372A have an on-chip 2-bit burst
counter. In the burst mode, the CY7C1370A and CY7C1372A
provide four cycles of data for a single address presented to
the SRAM. The order of the burst sequence is defined by the
MODE input pin. The MODE pin selects between linear and
interleaved burst sequence. The ADV/LD signal is used to load
a new external address (ADV/LD=LOW) or increment the in-
ternal burst counter (ADV/LD=HIGH)
Output enable (OE) and burst sequence select (MODE) are
the asynchronous signals. OE can be used to disable the out-
puts at any given time. ZZ may be tied to LOW if it is not used.
Four pins are used to implement JTAG test capabilities. The
JTAG circuitry is used to serially shift data to and from the
device. JTAG inputs use LVTTL/LVCMOS levels to shift data
during this testing mode of operation.
Functional Description
The CY7C1370A and CY7C1372A SRAMs are designed to
eliminate dead cycles when transitions from READ to WRITE
or vice versa. These SRAMs are optimized for 100 percent bus
utilization and achieve Zero Bus Latency. They integrate
524,288x36 and 1,048,576x18 SRAM cells, respectively, with
advanced synchronous peripheral circuitry and a 2-bit counter
for internal burst operation. The Synchronous Burst SRAM
family employs high-speed, low-power CMOS designs using
advanced triple-layer polysilicon, double-layer metal technolo-
gy. Each memory cell consists of four transistors and two high-
valued resistors.
Logic Block Diagram
CLK
CE
ADV/LD
A
x
CEN
CE
1
CE
2
CE
3
WE
BWS
x
Mode
CONTROL
and WRITE
LOGIC
256KX36/
512KX18
MEMORY
ARRAY
OUTOUT
REGISTERS
and LOGIC
D
Data-In REG.
Q
DQ
x
DP
x
CY7C1370
A
X
DQ
X
DP
X
BWS
X
X = 18:0
X = a, b, c, d
X = a, b, c, d
X = a, b, c, d
CY7C1372
X = 19:0
X = a, b
X = a, b
X = a, b
OE
.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
July 6, 2000
PRELIMINARY
Selection Guide
167 MHz
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
Shaded areas contain advance information.
CY7C1370A
CY7C1372A
150 MHz
3.8
310
30
133 MHz
4.2
280
30
100 MHz
5.0
250
30
3.4
Com’l
350
30
Pin Configurations
100-Pin TQFP Packages
A
A
CE
1
CE
2
BWSd
BWSc
BWSb
BWSa
CE
3
V
DD
V
SS
CLK
WE
CEN
OE
ADV/LD
A
A
A
A
CE
1
CE
2
NC
NC
BWSb
BWSa
CE
3
V
DD
V
SS
CLK
WE
CEN
OE
ADV/LD
A
A
DPb
DQb
DQb
V
DDQ
V
SS
A
A
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
DPc
DQc
DQc
V
DDQ
V
SS
DQc
DQc
DQc
DQc
V
SS
V
DDQ
DQc
DQc
NC
V
DD
V
DD
V
SS
DQd
DQd
V
DDQ
V
SS
DQd
DQd
DQd
DQd
V
SS
V
DDQ
DQd
DQd
DPd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1370A
(512K x 36)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
NC
V
DDQ
V
SS
NC
NC
DQb
DQb
V
SS
V
DDQ
DQb
DQb
NC
V
DD
V
DD
V
SS
DQb
DQb
V
DDQ
V
SS
DQb
DQb
DPb
NC
V
SS
V
DDQ
NC
NC
NC
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
DQb
DQb
DQb
DQb
V
SS
V
DDQ
DQb
DQb
V
SS
V
DD
V
DD
NC
DQa
DQa
V
DDQ
V
SS
DQa
DQa
DQa
DQa
V
SS
V
DDQ
DQa
DQa
DPa
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
A
A
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
V
DDQ
V
SS
NC
DPa
DQa
DQa
V
SS
V
DDQ
DQa
DQa
V
SS
V
DD
V
DD
NC
DQa
DQa
V
DDQ
V
SS
DQa
DQa
NC
NC
V
SS
V
DDQ
NC
NC
NC
CY7C1372A
(1M x 18)
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
MODE
A
A
A
A
A1
A0
DNU
DNU
V
SS
V
DD
DNU
DNU
A
A
A
A
A
A
A
MODE
A
A
A
A
A1
A0
DNU
DNU
V
SS
V
DD
2
DNU
DNU
A
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
PRELIMINARY
Pin Configurations
(continued)
119-Ball Bump BGA
CY7C1370A (512K x 36) - 7 x 17 BGA
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQc
DQc
V
DDQ
DQc
DQc
V
DDQ
DQd
DQd
V
DDQ
DQd
DQd
NC
64M
V
DDQ
CY7C1370A
CY7C1372A
2
A
NC
A
DPc
DQc
DQc
DQc
DQc
V
DD
DQd
DQd
DQd
DQd
DPd
A
NC
TMS
3
A
A
A
V
SS
V
SS
V
SS
BWSc
V
SS
V
DD(1)
V
SS
BWSd
V
SS
V
SS
V
SS
MODE
A
TDI
4
A
ADV/LD
V
DD
NC
CE
1
OE
A
WE
V
DD
CLK
NC
CEN
A1
A0
V
DD
A
TCK
5
A
A
A
V
SS
V
SS
V
SS
BWSb
V
SS
V
DD(1)
V
SS
BWSa
V
SS
V
SS
V
SS
NC
A
TDO
6
A
NC
A
DPb
DQb
DQb
DQb
DQ
b
V
DD
DQa
DQa
DQa
DQa
DPa
A
32M
DNU
7
V
DDQ
NC
NC
DQb
DQb
V
DDQ
DQb
DQb
V
DDQ
DQa
DQa
V
DDQ
DQa
DQa
NC
NC
V
DDQ
CY7C1372A (1M x 18) - 7 x 17 BGA
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQb
NC
V
DDQ
NC
DQb
V
DDQ
NC
DQb
V
DDQ
DQb
NC
NC
64M
V
DDQ
2
A
NC
A
NC
DQb
NC
DQb
NC
V
DD
DQb
NC
DQb
NC
DPb
A
A
TMS
3
A
A
A
V
SS
V
SS
V
SS
BWSb
V
SS
V
DD(1)
V
SS
V
SS
V
SS
V
SS
V
SS
MODE
A
TDI
4
A
ADV/LD
V
DD
NC
CE
1
OE
A
WE
V
DD
CLK
NC
CEN
A1
A0
V
DD
32M
TCK
5
A
A
A
V
SS
V
SS
V
SS
V
SS
V
SS
V
DD(1)
V
SS
BWSa
V
SS
V
SS
V
SS
NC
A
TDO
6
A
NC
A
DPa
NC
DQa
NC
DQa
V
DD
NC
DQa
NC
DQa
NC
A
A
DNU
7
V
DDQ
NC
NC
NC
DQa
V
DDQ
DQa
NC
V
DDQ
DQa
NC
V
DDQ
NC
DQa
NC
NC
V
DDQ
3
PRELIMINARY
Pin Definitions (100-Pin TQFP)
x18 Pin Location
37, 36, 32–35,
44–50, 80–84, 99,
100
93, 94
x36 Pin Location
37, 36, 32–35,
44–50, 81-84, 99,
100
93, 94, 95, 96
Name
A0
A1
A
BWSa
BWSb
BWSc
BWSd
WE
I/O Type
Input-
Synchronous
Input-
Synchronous
Description
CY7C1370A
CY7C1372A
Address Inputs used to select one of the 266,144 ad-
dress locations. Sampled at the rising edge of the CLK.
Byte Write Select Inputs, active LOW. Qualified with WE
to conduct writes to the SRAM. Sampled on the rising
edge of CLK. BWSa controls DQa and DPa, BWSb con-
trols DQb and DPb, BWSc controls DQc and DPc, BWSd
controls DQd and DPd.
Write Enable Input, active LOW. Sampled on the rising
edge of CLK if CEN is active LOW. This signal must be
asserted LOW to initiate a write sequence.
Advance/Load Input used to advance the on-chip ad-
dress counter or load a new address. When HIGH (and
CEN is asserted LOW) the internal burst counter is ad-
vanced. When LOW, a new address can be loaded into
the device for an access. After being deselected, ADV/LD
should be driven LOW in order to load a new address.
Clock Input. Used to capture all synchronous inputs to
the device. CLK is qualified with CEN. CLK is only rec-
ognized if CEN is active LOW.
Chip Enable 1 Input, active LOW. Sampled on the rising
edge of CLK. Used in conjunction with CE
2
and CE
3
to
select/deselect the device.
Chip Enable 2 Input, active HIGH. Sampled on the rising
edge of CLK. Used in conjunction with CE
1
and CE
3
to
select/deselect the device.
Chip Enable 3 Input, active LOW. Sampled on the rising
edge of CLK. Used in conjunction with CE
1
and CE
2
to
select/deselect the device.
88
88
Input-
Synchronous
Input-
Synchronous
85
85
ADV/LD
89
89
CLK
Input-Clock
98
98
CE
1
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
97
97
CE
2
92
92
CE
3
86
86
OE
Input-
Output Enable, active LOW. Combined with the synchro-
Asynchronous nous logic block inside the device to control the direction
of the I/O pins. When LOW, the I/O pins are allowed to
behave as outputs. When deasserted HIGH, I/O pins are
three-stated, and act as input data pins. OE is masked
during the data portion of a write sequence, during the
first clock when emerging from a deselected state and
when the device has been deselected.
Input-
Synchronous
Clock Enable Input, active LOW. When asserted LOW
the clock signal is recognized by the SRAM. When deas-
serted HIGH the clock signal is masked. Since deassert-
ing CEN does not deselect the device, CEN can be used
to extend the previous cycle when required.
Bidirectional Data I/O lines. As inputs, they feed into an
on-chip data register that is triggered by the rising edge
of CLK. As outputs, they deliver the data contained in the
memory location specified by A
[17:0]
during the previous
clock rise of the read cycle. The direction of the pins is
controlled by OE and the internal control logic. When OE
is asserted LOW, the pins can behave as outputs. When
HIGH, DQa–DQd are placed in a three-state condition.
The outputs are automatically three-stated during the
data portion of a write sequence, during the first clock
when emerging from a deselected state, and when the
device is deselected, regardless of the state of OE.
87
87
CEN
(a)58, 59, 62, 63,
68, 69, 72–73
(b)8, 9, 12, 13, 18,
19, 22–23
(a)52, 53, 56–59,
62, 63,
(b)68, 69, 72–75,
78, 79
(c)2, 3, 6–9, 12, 13,
(d)18, 19, 22–25,
28, 29
DQa
DQb
DQc
DQd
I/O-
Synchronous
4
PRELIMINARY
Pin Definitions (100-Pin TQFP)
(continued)
x18 Pin Location
74, 24
x36 Pin Location
51, 80, 1, 30
Name
DPa
DPb
DPc
DPd
MODE
I/O Type
I/O-
Synchronous
Description
CY7C1370A
CY7C1372A
Bidirectional Data Parity I/O lines. Functionally, these sig-
nals are identical to DQ[31:0]. During write sequences,
DPa is controlled by BWSa, DPb is controlled by BWSb,
DPc is controlled by BWSc, and DPd is controlled by
BWSd.
Mode Input. Selects the burst order of the device. Tied
HIGH selects the interleaved burst order. Pulled LOW
selects the linear burst order. MODE should not change
states during operation. When left floating MODE will de-
fault HIGH, to an interleaved burst order.
Power supply inputs to the core of the device.
Power supply for the I/O circuitry.
Ground for the device. Should be connected to ground of
the system.
No connects. Reserved for address expansion to 512K
depths.
Do Not Use pins. These pins should be left floating.
31
31
Input
Strap Pin
15, 16, 41, 65, 66,
91
4, 11, 20, 27, 54,
61, 70, 77
5, 10, 17, 21, 26,
40, 55, 60, 67, 71,
76, 90
14
38, 39, 42, 43
15, 16, 41, 65, 66,
91
4, 11, 20, 27, 54,
61, 70, 77
5, 10, 17, 21, 26,
40, 55, 60, 67, 71,
76, 90
14
38, 39, 42, 43
V
DD
V
DDQ
V
SS
Power Supply
I/O Power
Supply
Ground
NC
DNU
-
-
Pin Definitions (119 BGA)
x18 Pin Location
P4, N4, A2, A3, A4,
A5, A6, B3, B5, C2,
C3, C5, C6, G4, R2,
R6, T2, T3, T5, T6
L5, G3
x36 Pin Location
P4, N4, A2, A3, A4,
A5, A6, B3, B5, C2,
C3, C5, C6, R2, R6,
G4, T3, T4, T5
L5, G5, G3, L3
Name
A0
A1
A
BWSa
BWSb
BWSc
BWSd
WE
I/O Type
Input-
Synchronous
Description
Address Inputs used to select one of the 266,144
address locations. Sampled at the rising edge of the
CLK.
Byte Write Select Inputs, active LOW. Qualified with
WE to conduct writes to the SRAM. Sampled on the
rising edge of CLK. BWSa controls DQa and DPa,
BWSb controls DQb and DPb, BWSc controls DQc
and DPc, BWSd controls DQd and DPd.
Write Enable Input, active LOW. Sampled on the ris-
ing edge of CLK if CEN is active LOW. This signal
must be asserted LOW to initiate a write sequence.
Advance/Load Input used to advance the on-chip ad-
dress counter or load a new address. When HIGH
(and CEN is asserted LOW) the internal burst
counter is advanced. When LOW, a new address can
be loaded into the device for an access. After being
deselected, ADV/LD should be driven LOW in order
to load a new address.
Clock Input. Used to capture all synchronous inputs
to the device. CLK is qualified with CEN. CLK is only
recognized if CEN is active LOW.
Chip Enable 1 Input, active LOW. Sampled on the
rising edge of CLK.
Input-
Synchronous
H4
H4
Input-
Synchronous
Input-
Synchronous
B4
B4
ADV/LD
K4
K4
CLK
Input-Clock
E4
E4
CE
1
Input-
Synchronous
5
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