Latch-up Current...................................................... >200 mA
Operating Range
Range
Commercial
Industrial
Ambient
Temperature
0°C to +70°C
–40°C to +85°C
V
CC
3.3V
±
0.3V
DC Electrical Characteristics
Over the Operating Range
–10
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
I
SB1
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
[1]
Input Leakage Current
GND < V
I
< V
CC
Output Leakage Current GND < V
OUT
< V
CC
,
Output Disabled
V
CC
Operating
Supply Current
Automatic CE
Power-down Current
—TTL Inputs
Automatic CE
Power-down Current
—CMOS Inputs
V
CC
= Max.,
f = f
MAX
= 1/t
RC
Max. V
CC
, CE > V
IH
V
IN
> V
IH
or
V
IN
< V
IL
, f = f
MAX
Max. V
CC
,
CE > V
CC
– 0.3V,
V
IN
> V
CC
– 0.3V,
or V
IN
< 0.3V, f = 0
Com’l/
Ind’l
Com’l
Ind’l
Test Conditions
V
CC
= Min., I
OH
= –4.0 mA
V
CC
= Min., I
OL
= 8.0 mA
2.0
–0.3
–1
–1
Min.
2.4
0.4
V
CC
+ 0.3
0.8
+1
+1
90
100
40
2.0
–0.3
–1
–1
Max.
2.4
0.4
V
CC
+ 0.3
0.8
+1
+1
85
95
40
2.0
–0.3
–1
–1
–12
Min.
Max.
2.4
0.4
V
CC
+ 0.3
0.8
+1
+1
80
90
40
–15
Min.
Max.
Unit
V
V
V
V
µA
µA
mA
mA
mA
I
SB2
10
10
10
mA
Capacitance
[2]
Parameter
C
IN
C
OUT
Description
Input Capacitance
I/O Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz, V
CC
= 3.3V
Max.
8
8
Unit
pF
pF
Thermal Resistance
[2]
Parameter
Θ
JA
Θ
JC
Description
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Test Conditions
Still Air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
TSOP II
44.56
10.75
TQFP
42.66
14.64
VFBGA
46.98
9.63
Unit
°C/W
°C/W
Notes:
1. V
IL
(min.) = –2.0V for pulse durations of less than 20 ns.
2. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05232 Rev. *E
Page 3 of 11
CY7C1011CV33
AC Test Loads and Waveforms
[3]
10-ns devices:
OUTPUT
50
Ω
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
1.5V
12-, 15-ns devices:
Z = 50Ω
3.3V
R 317Ω
30 pF*
OUTPUT
30 pF
R2
351Ω
(a)
(b)
High-Z characteristics:
R 317Ω
3.0V
90%
GND
10%
ALL INPUT PULSES
90%
10%
3.3V
OUTPUT
5 pF
R2
351Ω
Rise Time: 1 V/ns
(c)
Fall Time: 1 V/ns
(d)
AC Switching Characteristics
Over the Operating Range
[4]
–10
Parameter
Read Cycle
t
power[5]
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
V
CC
(typical) to the first access
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z
OE HIGH to High-Z
[6, 7]
CE LOW to Low-Z
[7]
CE HIGH to High-Z
[6, 7]
CE LOW to Power-up
CE HIGH to Power-down
Byte Enable to Data Valid
Byte Enable to Low-Z
Byte Disable to High-Z
0
6
0
10
5
0
6
3
5
0
12
6
0
7
0
5
3
6
0
15
7
3
10
5
0
6
3
7
1
10
10
3
12
6
0
7
1
12
12
3
15
7
1
15
15
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
Min.
–12
Max.
Min.
–15
Max.
Unit
Notes:
3. AC characteristics (except High-Z) for all 10-ns parts are tested using the load conditions shown in (a). All other speeds are tested using the Thevenin load shown
in (b). High-Z characteristics are tested for all speeds using the test load shown in (d).
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
5. t
POWER
gives the minimum amount of time that the power supply should be at typical V
CC
values until the first memory access is performed.
6. t
HZOE
, t
HZCE
, and t
HZWE
are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads. Transition is measured
±
500 mV from steady-state voltage.
7. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
Document #: 38-05232 Rev. *E
Page 4 of 11
CY7C1011CV33
AC Switching Characteristics
Over the Operating Range
[4]
(continued)
–10
Parameter
Write Cycle
[8, 9]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
t
BW
Write Cycle Time
CE LOW to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE HIGH to Low-Z
[7]
WE LOW to High-Z
[6, 7]
Byte Enable to End of Write
7
10
7
7
0
0
7
5
0
3
5
8
12
8
8
0
0
8
6
0
3
6
10
15
10
10
0
0
10
7
0
3
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
Min.
–12
Max.
Min.
–15
Max.
Unit
Data Retention Waveform
DATA RETENTION MODE
V
CC
3.0V
t
CDR
CE
V
DR
> 2V
3.0V
t
R
Switching Waveforms
Read Cycle No. 1
[10, 11]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Notes:
8. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these
signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
9. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
10. Device is continuously selected. OE, CE, BHE and/or BHE = V
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