CY24C01/02/04/08/16
1 Kbit, 2 Kbit, 4 Kbit, 8 Kbit, and 16 Kbit (x8)
Two Wire (I2C) Serial EEPROM
Features
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Continuous voltage operation
❐
V
CC
= 1.65V to 5.5V
Internally organized as 128 x 8 (1K), 256 x 8 (2K), 512 x 8 (4K),
1024 x 8 (8K), or 2048 x 8 (16K)
Industry standard two wire serial interface
Schmitt trigger, filtered inputs for noise suppression
Bidirectional data transfer protocol
1 MHz (2.5V - 5.5V), 400 KHz (1.65V - 5.5V), and 100 KHz
(1.65V - 5.5V) compatibility
Write protect pin for hardware data protection
16-byte page write mode
Partial page writes enabled
Self timed write cycle (5 ms max)
High reliability
❐
Endurance: 1 million write cycles
❐
Data retention: 100 years
Industrial temperature range
8-Pin SOIC and 8-Pin TSSOP packages
Pb-free and RoHS compliant
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Functional Description
The CY24C01/02/04/08/16 range of products provide 1K, 2K,
4K, 8K, and 16K bits of serial Electrically Erasable and Program-
mable Read Only Memory (EEPROM) organized as 128, 256,
512, 1024, and 2048 words of eight bits each. The device is
optimized for use in many industrial applications where low
power and low voltage operations are essential. The
CY24C01/02/04/08/16 is available in space saving 8-Pin SOIC
and 8-Pin TSSOP packages and is accessed through a two-wire
serial interface. In addition, the entire family is available in 1.65V
(1.65V to 5.5V) version.
Logic Block Diagram
V
CC
SCL
SDA
CY24C01/02/04/08/16
A0–A2
WP
V
SS
Cypress Semiconductor Corporation
Document #: 001-15632 Rev. *C
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised February 05, 2009
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CY24C01/02/04/08/16
Pinouts
Figure 1. Pin Diagram - 8-Pin SOIC/TSSOP Package
A0
A1
A2
V
SS
1
2
8
7
V
CC
WP
SCL
SDA
Top View
3
4
(not to scale)
6
5
Table 1. Pin Definitions - 8-Pin SOIC/TSSOP Package
Pin
Name
A0–A2
8-SOIC/TSSOP
Pin Number
1,2,3
I/O Type
Input
Description
Device Address Pins.
The CY24C01 and CY24C02 uses the A2, A1, and A0
inputs for hard wire addressing and a total of eight 1K and 2K devices may be
addressed on a single bus system.
The CY24C04 uses the A2 and A1 inputs for hard wire addressing and a total of
four 4K devices may be addressed on a single bus system. The A0 pin is a no
connect.
The CY24C08 uses only the A2 input for hardwire addressing and a total of two
8K devices may be addressed on a single bus system. The A0 and A1 pins are
no connects.
The CY24C16 does not use the device address pins which limit the number of
devices on a single bus to one. The A0, A1, and A2 pins are no connects.
Ground.
The ground for the device. It must be connected to the ground of the
system.
Serial Data.
The SDA pin is bidirectional for serial data transfer. This pin is open
drain driven and is wired-ORed with any number of other open drain or open
collector devices.
Serial Clock.
The SCL input is used to positive edge clock data into each
EEPROM device and negative edge clock data out of each device.
Write Protect.
The CY24C01/02/04/08/16 has a write protect pin that provides
hardware data protection. The write protect pin allows normal read and write
operations when connected to ground (GND). When the write protect pin is
connected to VCC, the write protection feature is enabled and operates as shown
in
Table 2
on page 3.
Power Supply.
The power supply inputs to the device.
V
SS
SDA
4
5
Ground
Input/Output
SCL
WP
6
7
Input
Input
V
CC
8
Power Supply
Document #: 001-15632 Rev. *C
Page 2 of 16
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CY24C01/02/04/08/16
Memory Organization
CY24C01
Internally organized with eight pages of 16 bytes each, the 1K
requires a 7-bit data word address for random word addressing.
Stop Condition
A low to high transition of SDA with SCL high is a stop condition.
After a read sequence, the stop command places the EEPROM
in a standby power mode (see
Figure 2).
CY24C02
Internally organized with 16 pages of 16-bytes each, the 2K
requires a 8-bit data word address for random word addressing.
Acknowledge
All addresses and data words are serially transmitted to and from
the EEPROM in 8-bit words. The EEPROM acknowledges each
word received by sending a zero during the ninth clock cycle.
CY24C04
Internally organized with 32 pages of 16 bytes each, the 4K
requires a 9-bit data word address for random word addressing.
Standby Mode
The CY24C01/02/04/08/16 features a low power standby mode,
which is enabled on power up, after the receipt of the STOP bit
and the completion of any internal operations.
CY24C08
Internally organized with 64 pages of 16 bytes each, the 8K
requires a 10-bit data word address for random word addressing.
Device Internal Reset
To prevent inadvertent write operations during power up, a
Power On Reset (POR) circuit is included. During power up
(continuous rise of V
CC
), the device does not respond to any
instruction until the V
CC
reaches the POR threshold voltage (this
threshold is lower than the V
CC
minimum operating voltage
defined in
DC Electrical Characteristics
on page 8). When V
CC
has passed over the POR threshold, the device is reset and is in
standby power mode. During power down (continuous decay of
V
CC
), when V
CC
drops from the normal operating voltage to
below the POR threshold voltage, the device stops responding
to any instruction sent to it. Before selecting and issuing instruc-
tions to the memory, a valid and stable V
CC
voltage must be
applied. This voltage must remain stable and valid until the end
of the transmission of the instruction and, for a write instruction,
until the completion of the internal write cycle (t
WR
).
CY24C16
Internally organized with 128 pages of 16 bytes each, the 16K
requires an 11-bit data word address for random word
addressing.
Device Operating Features
Clock and Data Transitions
The SDA pin is normally pulled high with an external device. Data
on the SDA pin changes only during SCL low time periods. Data
changes during SCL high periods indicate a start or stop
condition as defined in the following section.
Start Condition
A high to low transition of SDA with SCL high is a start condition
which must precede any other command (see
Figure 2).
Memory Reset
After an interruption in protocol, power loss, or system reset, any
two-wire part is reset with the following steps:
1. Clock up to nine cycles.
2. Look for SDA high in each cycle while SCL is high.
3. Create a start condition as SDA is high.
Table 2. Write Protect
WP Pin Status
V
CC
V
SS
Part of the Memory Protected
CY24C01
Full 1K Array
CY24C02
Full 2K Array
CY24C04
Full 4K Array
Normal Read/Write Operations
Figure 2. Start/Stop Definition
CY24C08
Full 8K Array
CY24C16
Full 16K Array
SCL
SDA
S T A R T B IT
S T O P B IT
Document #: 001-15632 Rev. *C
Page 3 of 16
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CY24C01/02/04/08/16
Figure 3. Acknowledge Timing
SCL
1
8
9
Data In
Data Out
Start
Acknowledge
Device Addressing
The CY24C01/02/04/08/16 EEPROM requires an 8-bit device
address word after a start condition, to enable the chip for a read
or write operation (refer to
Table 3
on page 5).
The device address word consists of a mandatory one, zero
sequence for the first four most significant bits as shown in
Table 3
on page 5. This is common to all the EEPROM devices.
The next three bits are the A2, A1, and A0 device address bits
for CY24C01 and CY24C02. These three bits must compare to
their corresponding hard wired input pins.
CY24C04 uses only the A2 and A1 device address bits. The third
bit is a memory page address bit. The two device address bits
must compare to their corresponding hard wired input pins. The
A0 pin is no connect.
CY24C08 only uses the A2 device address bit with the next 2 bits
being for memory page addressing. The A2 bit must compare to
its corresponding hard wired input pin. The A1 and A0 pins are
no connect.
CY24C16 does not use any device address bits and the 3 bits
are used for memory page addressing. The page addressing bits
on the 4K, 8K, and 16K devices must be considered the most
significant bits of the data word address which follows. The A0,
A1, and A2 pins are no connect.
The eighth bit of the device address is the read or write operation
select bit. A read operation is initiated if this bit is high and a write
operation is initiated if this bit is low.
When the device address is compared, the EEPROM outputs a
zero. If a compare is not made, the chip returns to the standby
state.
Write Operations
Byte Write
A write operation requires an 8-bit data word address following
the device address word and acknowledgment. On receipt of this
address, the EEPROM responds with a zero and then clocks in
the first 8-bit data word. Following the receipt of the 8-bit data
word, the EEPROM outputs a zero. The addressing device, such
as a microcontroller, must terminate the write sequence with a
stop condition. At this time the EEPROM enters an internally
timed write cycle, t
WR
, to the nonvolatile memory. All inputs are
disabled during this write cycle and the EEPROM does not
respond until the write is complete (see
Figure 4
on page 6).
Page Write
The CY24C01/02/04/08/16/CY24C08/CY24C16 devices are
capable of 16-byte page writes.
A page write is initiated in the same way as a byte write, but the
microcontroller does not send a stop condition after the first data
word is clocked in. Instead, after the EEPROM acknowledges
receipt of the first data word, the microcontroller can transmit up
to 15 more data words. The EEPROM responds with a zero after
each data word is received. The microcontroller must terminate
the page write sequence with a stop condition
(see
Figure 5
on page 6).
The lower four bits of the data word address are internally
incremented following the receipt of each data word. The higher
data word address bits are not incremented, retaining the
memory page row location. When the internally generated word
address reaches the page boundary, the next byte is placed at
the beginning of the same page. If more than 16 data words are
transmitted to the EEPROM, the data word address rolls over
and the previous data is overwritten.
Acknowledge Polling
When the internally timed write cycle has started and the
EEPROM inputs are disabled, acknowledge polling is initiated.
This involves sending a start condition followed by the device
address word. The read or write bit is representative of the
operation desired. After the internal write cycle is complete, the
EEPROM responds with a zero, enabling the read or write
sequence to continue.
Document #: 001-15632 Rev. *C
Page 4 of 16
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CY24C01/02/04/08/16
Read Operations
Read operations are initiated in the same way as write opera-
tions except that the read or write select bit in the device address
word is set to one. There are three read operations: current
address read, random address read, and sequential read.
Random Read
A random read needs a ‘dummy’ byte write sequence to load in
the data word address. After the device address word and data
word address are clocked in and acknowledged by the
EEPROM, the microcontroller must generate another start
condition. The microcontroller initiates a current address read by
sending a device address with the read or write select bit high.
The EEPROM acknowledges the device address and serially
clocks out the data word. The microcontroller does not respond
with a zero but generates a stop condition as shown in
Figure 7
on page 6.
Current Address Read
The internal data word address counter maintains the last
address accessed during the last read or write operation, incre-
mented by one. This address stays valid between operations as
long as the chip power is maintained. The address roll over
during read and byte write is from the last byte of the last memory
page to the first byte of the first page. The address roll over
during write is from the last byte of the current page to the first
byte of the same page. After the device address with the read or
write select bit set to one is clocked in and acknowledged by the
EEPROM, the current address data word is serially clocked out.
The microcontroller does not respond with an input zero but
generates a stop condition (see
Figure 6
on page 6).
Sequential Read
Sequential reads are initiated by either a current address read or
a random address read. After the microcontroller receives a data
word, it responds with an acknowledgement. As long as the
EEPROM receives an acknowledgement, it continues to
increment the data word address and serially clocks out
sequential data words. When the address memory limit is
reached, the data word address rolls over and the sequential
read continues. The sequential read operation is terminated
when the microcontroller does not respond with a zero but
generates a stop condition (see
Figure 8
on page 7).
Table 3. Device Addressing
[1,2,3]
Density
1K/2K
4K
8K
16K
Device Type Identifier
b7
1
1
1
1
b6
0
0
0
0
b5
1
1
1
1
b4
0
0
0
0
b3
A2
A2
A2
P2
Chip Enable Address
b2
A1
A1
P1
P1
b1
A0
P0
P0
P0
b0
R/W
R/W
R/W
R/W
Table 4. Operating Modes
Mode
Current Address Read
Random Address Read
Sequential Read
Byte Write
Page Write
R/W Bit
1
0
1
1
0
0
WP
X
X
X
X
0
0
>1
1
<16
Bytes
1
1
Initial Sequence
Start, Device Select, R/W = 1
Start, Device Select, R/W = 0, Address
reStart, Device Select, R/W = 1
Similar to Current or Random Address Read
Start, Device Select, R/W = 0
Start, Device Select, R/W = 0
Notes
1. P2, P1, P0 are used for memory page addressing.
2. A2, A1 and A0 are compared against the respective external pins on the memory device.
3. The MSB b7 is sent first.
Document #: 001-15632 Rev. *C
Page 5 of 16
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