PRELIMINARY
CY7C1371A
CY7C1373A
512Kx36/1Mx18 Flow-Thru SRAM with NoBL™ Architecture
Features
•
Pin compatible and functionally equivalent to ZBT de-
vices
• Supports 117-MHz bus operations with zero wait states
— Data is transferred on every clock
• Internally self-timed output buffer control to eliminate
the need to use asynchronous OE
• Registered inputs for Flow-Through operation
• Byte Write capability
• Common I/O architecture
• 3.3V (-5% / +10%) power supply
• Fast clock-to-output times
— 7.5 ns (for 117-MHz device)
— 8.5 ns (for 100-MHz device)
— 9.0 ns (for 83-MHz device)
•
•
•
•
— 10.0 ns (for 66-MHz device)
Clock Enable (CEN) pin to suspend operation
Synchronous self-timed writes
Available in 100 TQFP & 119 BGA Packages
Burst Capability - linear or interleaved burst order
signed specifically to support unlimited true back-to-back
Read/Write operations without the insertion of wait states. The
CY7C1371A/CY7C1373A is equipped with the advanced No
Bus Latency™ (NoBL) logic required to enable consecutive
Read/Write operations with data being transferred on every
clock cycle. This feature dramatically improves the throughput
of data through the SRAM, especially in systems that require
frequent
Write/Read
transitions.
The
CY7C1371A/
CY7C1373A is pin compatible and functionally equivalent to
ZBT devices.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock.The clock input is qualified by
the Clock Enable (CEN) signal, which when deasserted sus-
pends operation and extends the previous clock cycle. Maxi-
mum access delay from the clock rise is 7.5 ns (117-MHz de-
vice).
Write operations are controlled by the Byte Write Selects
(BWS
a,b,c,d
for CY7C1371A and BWS
a,b
for CY7C1373A) and
a Write Enable (WE) input. All writes are conducted with on-
chip synchronous self-timed write circuitry.
Synchronous Chip Enable(s) (CE
1
, CE
2
, CE
3
on TQFP, CE
1
on BGA) and an asynchronous Output Enable (OE) provide for
easy bank selection and output three-state control. In order to
avoid bus contention, the output drivers are synchronously
three-stated during the data portion of a write sequence.
Functional Description
The CY7C1371A and CY7C1373A are 512K by 36 and 1M by
18 Synchronous-Flow-Through Burst SRAMs respectively de-
Logic Block Diagram
CLK
CE
ADV/LD
A
x
CEN
CE
1
CE2
CE3
WE
BWS
x
Mode
CONTROL
and WRITE
LOGIC
256KX36/
512KX18
MEMORY
ARRAY
D
Data-In REG.
Q
AX
DQX
CY7C1371
X = 18:0
CY7C1373
X = 19:0
DQ
x
DP
x
X= a, b, c, d X = a, b
DPX X = a, b, c, d X = a, b
BWSX X = a, b, c, d X = a, b
OE
.
Selection Guide
7C1371A-117
7C1373A-117
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
Com’l
Com’l
7.5
250
30
7C1371A-100
7C1373A-100
8.5
230
30
7C1371A-83
7C1373A-83
9.0
215
30
7C1371A-66
7C1373A-66
10.0
180
30
Shaded areas contain advance information.
ZBT is a trademark of Integrated Device Technology.
No Bus Latency and NoBL are trademarks of Cypress Semiconductor Corporation.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
July 6, 2000
PRELIMINARY
Pin Configurations
100-Pin TQFP Packages
CY7C1371A
CY7C1373A
A
A
CE
1
CE
2
BWSd
BWSc
BWSb
BWSa
CE
3
V
DD
V
SS
CLK
WE
CEN
OE
ADV/LD
NC
A
A
A
CE
1
CE
2
NC
NC
BWSb
BWSa
CE
3
V
DD
V
SS
CLK
WE
CEN
OE
ADV/LD
NC
A
NC
NC
NC
V
DDQ
V
SS
NC
NC
DQb
DQb
V
SS
V
DDQ
DQb
DQb
Vss
V
DD
V
DD
V
SS
DQb
DQb
V
DDQ
V
SS
DQb
DQb
DPb
NC
V
SS
V
DDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
A
A
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
DPb
DQb
DQb
V
DDQ
V
SS
DQb
DQb
DQb
DQb
V
SS
V
DDQ
DQb
DQb
V
SS
V
DD
V
DD
NC
DQa
DQa
V
DDQ
V
SS
DQa
DQa
DQa
DQa
V
SS
V
DDQ
DQa
DQa
DPa
A
A
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
V
DDQ
V
SS
NC
DPa
DQa
DQa
V
SS
V
DDQ
DQa
DQa
V
SS
V
DD
V
DD
NC
DQa
DQa
V
DDQ
V
SS
DQa
DQa
NC
NC
V
SS
V
DDQ
NC
NC
NC
DPc
DQc
DQc
V
DDQ
V
SS
DQc
DQc
DQc
DQc
V
SS
V
DDQ
DQc
DQc
V
SS
V
DD
V
DD
V
SS
DQd
DQd
V
DDQ
V
SS
DQd
DQd
DQd
DQd
V
SS
V
DDQ
DQd
DQd
DPd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1371A
(512K x 36)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
CY7C1373A
(1M x 18)
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
MODE
A
A
A
A
A
1
A
0
DNU
DNU
V
SS
V
DD
DNU
DNU
A
A
A
A
A
A
MODE
A
A
A
A
A
1
A
0
DNU
DNU
V
SS
V
DD
DNU
DNU
A
A
A
A
A
A
A
2
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
PRELIMINARY
Pin Configurations
(continued)
119-Ball Bump BGA
CY7C1371A (512K x 36) - 7 x 17 BGA
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQc
DQc
V
DDQ
DQc
DQc
V
DDQ
DQd
DQd
V
DDQ
DQd
DQd
NC
NC
V
DDQ
CY7C1371A
CY7C1373A
2
A
NC
A
DPc
DQc
DQc
DQc
DQc
V
DD
DQd
DQd
DQd
DQd
DPd
A
64M
TMS
3
A
A
A
V
SS
V
SS
V
SS
BWSc
V
SS
V
SS(1)
V
SS
BWSd
V
SS
V
SS
V
SS
MODE
A
TDI
4
16M
ADV/LD
V
DD
NC
CE1
OE
A
WE
V
DD
CLK
NC
CEN
A1
A0
V
DD
A
TCK
5
A
A
A
V
SS
V
SS
V
SS
BWSb
V
SS
V
SS(1)
V
SS
BWSa
V
SS
V
SS
V
SS
V
SS
A
TDO
6
A
NC
A
DPb
DQb
DQb
DQb
DQb
V
DD
DQa
DQa
DQa
DQa
DPa
A
32M
DNU
7
V
DDQ
NC
NC
DQb
DQb
V
DDQ
DQb
DQb
V
DDQ
DQa
DQa
V
DDQ
DQa
DQa
NC
NC
V
DDQ
CY7C1373A (1M x 18) - 7 x 17 BGA
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQb
NC
V
DDQ
NC
DQb
V
DDQ
NC
DQb
V
DDQ
DQb
NC
NC
64M
V
DDQ
2
A
NC
A
NC
DQb
NC
DQb
NC
V
DD
DQb
NC
DQb
NC
DPb
A
A
TMS
3
A
A
A
V
SS
V
SS
V
SS
BWSb
V
SS
V
SS(1)
V
SS
V
SS
V
SS
V
SS
V
SS
MODE
A
TDI
4
16M
ADV/LD
V
DD
NC
CE1
OE
A
WE
V
DD
CLK
NC
CEN
A1
A0
V
DD
32M
TCK
5
A
A
A
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS(1)
V
SS
BWSa
V
SS
V
SS
V
SS
V
ss
A
TDO
6
A
NC
A
DPa
NC
DQa
NC
DQa
V
DD
NC
DQa
NC
DQa
NC
A
A
DNU
7
V
DDQ
NC
NC
NC
DQa
V
DDQ
DQa
NC
V
DDQ
DQa
NC
V
DDQ
NC
DQa
NC
NC
V
DDQ
3
PRELIMINARY
Pin Definitions (100-Pin TQFP)
x18 Pin Location
37, 36, 32–35,
44–50,80–83, 99,
100
93, 94
x36 Pin Location
37, 36, 32–35,
44–50, 81–83, 99,
100
93, 94, 95, 96
Name
A0
A1
A
BWSa
BWSb
BWSc
BWSd
WE
I/O Type
Input-
Synchronous
Input-
Synchronous
Description
CY7C1371A
CY7C1373A
Address Inputs used to select one of the 266,144 address
locations. Sampled at the rising edge of the CLK.
Byte Write Select Inputs, active LOW. Qualified with WE
to conduct writes to the SRAM. Sampled on the rising
edge of CLK. BWSa controls DQa and DPa, BWSb con-
trols DQb and DPb, BWSc controls DQc and DPc, BWSd
controls DQd and DPd.
Write Enable Input, active LOW. Sampled on the rising
edge of CLK if CEN is active LOW. This signal must be
asserted LOW to initiate a write sequence.
Advance/Load input used to advance the on-chip address
counter or load a new address. When HIGH (and CEN is
asserted LOW) the internal burst counter is advanced.
When LOW, a new address can be loaded into the device
for an access. After being deselected, ADV/LD should be
driven LOW in order to load a new address.
Clock Input. Used to capture all synchronous inputs to the
device. CLK is qualified with CEN. CLK is only recognized
if CEN is active LOW.
Chip Enable 1 Input, active LOW. Sampled on the rising
edge of CLK. Used in conjunction with CE
2
and CE
3
to
select/deselect the device.
Chip Enable 2 Input, active HIGH. Sampled on the rising
edge of CLK. Used in conjunction with CE
1
and CE
3
to
select/deselect the device.
Chip Enable 3 Input, active LOW. Sampled on the rising
edge of CLK. Used in conjunction with CE
1
and CE
2
to
select/deselect the device.
88
88
Input-
Synchronous
Input-
Synchronous
85
85
ADV/LD
89
89
CLK
Input-Clock
98
98
CE
1
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
97
97
CE
2
92
92
CE
3
86
86
OE
Input-
Output Enable, active LOW. Combined with the synchro-
Asynchronous nous logic block inside the device to control the direction
of the I/O pins. When LOW, the I/O pins are allowed to
behave as outputs. When deasserted HIGH, I/O pins are
three-stated, and act as input data pins. OE is masked
during the data portion of a write sequence, during the
first clock when emerging from a deselected state and
when the device has been deselected.
Input-
Synchronous
Clock Enable Input, active LOW. When asserted LOW the
clock signal is recognized by the SRAM. When deassert-
ed HIGH the clock signal is masked. Since deasserting
CEN does not deselect the device, CEN can be used to
extend the previous cycle when required.
Bidirectional Data I/O lines. As inputs, they feed into an
on-chip data register that is triggered by the rising edge
of CLK. As outputs, they deliver the data contained in the
memory location specified by A
[17:0]
during the previous
clock rise of the read cycle. The direction of the pins is
controlled by OE and the internal control logic. When OE
is asserted LOW, the pins can behave as outputs. When
HIGH, DQa–DQd are placed in a three-state condition.
The outputs are automatically three-stated during the
data portion of a write sequence, during the first clock
when emerging from a deselected state, and when the
device is deselected, regardless of the state of OE.
87
87
CEN
(a)58, 59, 62, 63,
68, 69, 72–74,
(b)8, 9, 12, 13, 18,
19, 22–24
(a)52, 53, 56–59,
62, 63,
(b)68, 69, 72–75,
78, 79,
(c)2, 3, 6–9, 12, 13,
(d)18, 19, 22–25,
28, 29
DQa
DQb
DQc
DQd
I/O-
Synchronous
4
PRELIMINARY
Pin Definitions (100-Pin TQFP)
(continued)
x18 Pin Location
74, 24
x36 Pin Location
51, 80, 1, 30
Name
DPa
DPb
DPc
DPd
MODE
I/O Type
I/O-
Synchronous
Description
CY7C1371A
CY7C1373A
Bidirectional Data Parity I/O lines. Functionally, these sig-
nals are identical to DQ
[31:0]
. During write sequences,
DPa is controlled by BWSa, DPb is controlled by BWSb,
DPc is controlled by BWSc, and DPd is controlled by
BWSd.
Mode Input. Selects the burst order of the device. Tied
HIGH selects the interleaved burst order. Pulled LOW se-
lects the linear burst order. MODE should not change
states during operation. When left floating MODE will de-
fault HIGH, to an interleaved burst order.
Power supply inputs to the core of the device.
Power supply for the I/O circuitry.
Ground for the device. Should be connected to ground of
the system.
No connects. Reserved for address expansion to 512K
depths.
Do Not Use pins. These pins should be left floating.
31
31
Input
Strap pin
15, 41, 65, 66, 91
4, 11, 20, 27, 54,
61, 70, 77
5, 10, 14, 17, 21,
26, 40, 55, 60, 67,
71, 76, 90
64, 84
15, 41, 65, 66, 91
4, 11, 20, 27, 54,
61, 70, 77
5, 10, 14,17, 21, 26,
40, 55, 60, 67, 71,
76, 90
1–3, 6, 7, 25,
28–30, 51–53, 64,
75, 78, 79
38, 39, 42, 43
V
DD
V
DDQ
V
SS
Power Supply
I/O Power
Supply
Ground
NC
-
38, 39, 42, 43
DNU
-
5
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