CAT28C257
256 kb CMOS Parallel
EEPROM
Description
The CAT28C257 is a fast, low power, 5 V−only CMOS Parallel
EEPROM organized as 32K x 8−bits. It requires a simple interface for
in−system programming. On−chip address and data latches,
self−timed write cycle with auto−clear and V
CC
power up/down write
protection eliminate additional timing and protection hardware. DATA
Polling and Toggle status bits signal the start and end of the self−timed
write cycle. Additionally, the CAT28C257 features hardware and
software write protection.
The CAT28C257 is manufactured using ON Semiconductor’s
advanced CMOS floating gate technology. It is designed to endure
100,000 program/erase cycles and has a data retention of 100 years.
The device is available in JEDEC approved 28−pin DIP or 32−pin
PLCC packages.
Features
http://onsemi.com
PDIP−28
P, L SUFFIX
CASE 646AE
PLCC−32
N, G SUFFIX
CASE 776AK
PIN FUNCTION
Pin Name
A
0
−A
14
I/O
0
−I/O
7
CE
OE
WE
V
CC
V
SS
NC
Function
Address Inputs
Data Inputs/Outputs
Chip Enable
Output Enable
Write Enable
5 V Supply
Ground
No Connect
•
Fast Read Access Times: 120/150 ns
•
Low Power CMOS Dissipation:
•
•
•
•
•
•
•
•
•
– Active: 25 mA Max.
– Standby: 150
mA
Max.
Simple Write Operation:
– On−chip Address and Data Latches
– Self−timed Write Cycle with Auto−clear
Fast Write Cycle Time:
−
5 ms Max.
CMOS and TTL Compatible I/O
Automatic Page Write Operation:
−
1 to 128 Bytes in 5 ms
−
Page Load Timer
End of Write Detection:
−
Toggle Bit
−
DATA Polling
Hardware and Software Write Protection
100,000 Program/Erase Cycles
100 Year Data Retention
Commercial, Industrial and Automotive Temperature Ranges
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 13 of this data sheet.
©
Semiconductor Components Industries, LLC, 2009
December, 2009
−
Rev. 6
1
Publication Order Number:
CAT28C257/D
CAT28C257
PIN CONFIGURATION
DIP Package (P, L)
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
WE
A
13
A
8
A
9
A
11
OE
A
10
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
PLCC Package (N, G)
A
7
A
12
A
14
NC
V
CC
WE
A
13
A
6
A
5
A
4
A
3
A
2
A
1
A
0
NC
I/O
0
4 3 2 1 32 31 30
5
29
6
28
7
27
8
26
9
25
10
24
11
23
12
22
13
21
14 1516 171819 20
I/O
1
I/O
2
V
SS
NC
I/O
3
I/O
4
I/O
5
(Top Views)
A
8
A
9
A
11
NC
OE
A
10
CE
I/O
7
I/O
6
A
7
−A
14
ADDR. BUFFER
& LATCHES
INADVERTENT
WRITE
PROTECTION
ROW
DECODER
32,768 x 8
EEPROM
ARRAY
V
CC
HIGH VOLTAGE
GENERATOR
128 BYTE PAGE
REGISTER
CE
OE
WE
CONTROL
LOGIC
DATA POLLING
AND
TOGGLE BIT
COLUMN
DECODER
I/O BUFFERS
TIMER
ADDR. BUFFER
& LATCHES
I/O
0
−I/O
7
A
0
−A
6
Figure 1. Block Diagram
http://onsemi.com
2
CAT28C257
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters
Temperature Under Bias
Storage Temperature
Voltage on Any Pin with Respect to Ground (Note 1)
V
CC
with Respect to Ground
Package Power Dissipation Capability (T
A
= 25°C)
Lead Soldering Temperature (10 secs)
Output Short Circuit Current (Note 2)
Ratings
–55 to +125
–65 to +150
–2.0 V to +V
CC
+ 2.0 V
−2.0
to +7.0
1.0
300
100
Units
°C
°C
V
V
W
°C
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The minimum DC input voltage is
−0.5
V. During transitions, inputs may undershoot to
−2.0
V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+ 0.5 V, which may overshoot to V
CC
+ 2.0 V for periods of less than 20 ns.
2. Output shorted for no more than one second. No more than one output shorted at a time.
Table 2. RELIABILITY CHARACTERISTICS
(Note 3)
Symbol
N
END
T
DR
V
ZAP
I
LTH
(Note 4)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch−Up
Test Method
MIL−STD−883, Test Method 1033
MIL−STD−883, Test Method 1008
MIL−STD−883, Test Method 3015
JEDEC Standard 17
Min
10
4
or 10
5
100
2,000
100
Typ
Max
Units
Cycles/Byte
Years
V
mA
3. These parameters are tested initially and after a design or process change that affects the parameters.
4. Latch−up protection is provided for stresses up to 100 mA on address and data pins from
−1
V to V
CC
+ 1 V.
Table 3. D.C. OPERATING CHARACTERISTICS
(V
CC
= 5 V
±10%,
unless otherwise specified.)
Limits
Symbol
I
CC
I
CCC
(Note 5)
I
SB
I
SBC
(Note 6)
I
LI
I
LO
V
IH
(Note 6)
V
IL
(Note 5)
V
OH
V
OL
V
WI
Parameter
V
CC
Current (Operating, TTL)
V
CC
Current (Operating, CMOS)
V
CC
Current (Standby, TTL)
V
CC
Current (Standby, CMOS)
Input Leakage Current
Output Leakage Current
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Write Inhibit Voltage
I
OH
=
−400
mA
I
OL
= 2.1 mA
3.5
Test Conditions
CE = OE = V
IL
,
f = 6 MHz, All I/O’s Open
CE = OE = V
ILC
,
f = 6 MHz, All I/O’s Open
CE = V
IH
, All I/O’s Open
CE = V
IHC
, All I/O’s Open
V
IN
= GND to V
CC
V
OUT
= GND to V
CC
,
CE = V
IH
−10
−10
2
−0.3
2.4
0.4
Min
Typ
Max
30
25
1
150
10
10
V
CC
+ 0.3
0.8
Units
mA
mA
mA
mA
mA
mA
V
V
V
V
V
5. V
ILC
=
−0.3
V to +0.3 V
6. V
IHC
= V
CC
−0.3
V to V
CC
+ 0.3 V
http://onsemi.com
3
CAT28C257
Table 4. MODE SELECTION
Mode
Read
Byte Write (WE Controlled)
Byte Write (CE Controlled)
Standby and Write Inhibit
Read and Write Inhibit
H
X
CE
L
L
L
X
H
WE
H
OE
L
H
H
X
H
I/O
D
OUT
D
IN
D
IN
High−Z
High−Z
Power
ACTIVE
ACTIVE
ACTIVE
STANDBY
ACTIVE
Table 5. CAPACITANCE
(T
A
= 25°C, f = 1.0 MHz, V
CC
= 5 V)
Symbol
C
I/O
(Note 7)
C
IN
(Note 7)
Test
Input/Output Capacitance
Input Capacitance
Min
Typ
Max
10
6
Conditions
V
I/O
= 0 V
V
IN
= 0 V
Units
pF
pF
7. This parameter is tested initially and after a design or process change that affects the parameter.
Table 6. A.C. CHARACTERISTICS, READ CYCLE
(V
CC
= 5 V
±10%,
unless otherwise specified.)
28C257−12
Symbol
t
RC
t
CE
t
AA
t
OE
t
LZ
(Note 8)
t
OLZ
(Note 8)
t
HZ
(Notes 8, 9)
t
OHZ
(Notes 8, 9)
t
OH
(Note 8)
Parameter
Read Cycle Time
CE Access Time
Address Access Time
OE Access Time
CE Low to Active Output
OE Low to Active Output
CE High to High−Z Output
OE High to High−Z Output
Output Hold from Address Change
0
0
0
50
50
0
Min
120
120
120
50
0
0
50
50
Typ
Max
Min
150
150
150
70
28C257−15
Typ
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
8. This parameter is tested initially and after a design or process change that affects the parameter.
9. Output floating (High−Z) is defined as the state when the external data line is no longer driven by the output buffer.
Table 7. POWER−UP TIMING
Symbol
t
PUR
t
PUW
Power−Up to Read
Power−Up to Write
5
Parameter
Min
Typ
Max
100
10
Units
ms
ms
http://onsemi.com
4
CAT28C257
Table 8. A.C. CHARACTERISTICS, WRITE CYCLE
(V
CC
= 5 V
±10%,
unless otherwise specified.)
28C257−12
Symbol
t
WC
t
AS
t
AH
t
CS
t
CH
t
CW
(Note 10)
t
OES
t
OEH
t
WP
(Note 10)
t
DS
t
DH
t
INIT
(Note 11)
t
BLC
(Notes 11, 12)
Parameter
Write Cycle Time
Address Setup Time
Address Hold Time
CE Setup Time
CE Hold Time
CE Pulse Time
OE Setup Time
OE Hold Time
WE Pulse Width
Data Setup Time
Data Hold Time
Write Inhibit Period After Power−up
Byte Load Cycle Time
0
50
0
0
100
0
0
100
50
0
5
0.1
0
10
100
5
0.1
10
100
Min
Typ
Max
5
0
50
0
0
100
0
0
100
50
Min
28C257−15
Typ
Max
5
Units
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
10. A write pulse of less than 20 ns duration will not initiate a write cycle.
11. This parameter is tested initially and after a design or process change that affects the parameter.
12. A timer of duration t
BLC
max. begins with every LOW to HIGH transition of WE. If allowed to time out, a page or byte write will begin; however
a transition from HIGH to LOW within t
BLC
max. stops the timer.
V
CC
−
0.3 V
INPUT PULSE LEVELS
0.0 V
2.0 V
0.8 V
REFERENCE POINTS
Figure 2. A.C. Testing Input/Output Waveform
(Note 13)
13. Input rise and fall times (10% and 90%) < 10 ns.
1.3 V
1N914
3.3 K
DEVICE
UNDER
TEST
OUT
C
L
= 100 pF
C
L
INCLUDES JIG CAPACITANCE
Figure 3. A.C. Testing Load Circuit (example)
http://onsemi.com
5
DSP 与 ARM 处理器
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
