CMLDM8120TG
SURFACE MOUNT
P-CHANNEL
ENHANCEMENT-MODE
SILICON MOSFET
w w w. c e n t r a l s e m i . c o m
DESCRIPTION:
The CENTRAL SEMICONDUCTOR CMLDM8120TG
is an Enhancement-mode P-Channel Field Effect
Transistor, manufactured by the P-Channel DMOS
Process, designed for high speed pulsed amplifier and
driver applications. This MOSFET offers Low rDS(ON)
and a MAX Threshold Voltage of 0.85V.
MARKING CODE: CT8
SOT-563 CASE
APPLICATIONS:
•
Load/Power switches
•
Power supply converter circuits
•
Battery powered portable equipment
MAXIMUM RATINGS:
(TA=25°C)
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current (Steady State)
Continuous Drain Current, t≤5.0s
Continuous Source Current (Body Diode)
Maximum Pulsed Drain Current, tp=10μs
Maximum Pulsed Source Current, tp=10μs
Power Dissipation (Note 1)
Power Dissipation (Note 2)
Power Dissipation (Note 3)
Operating and Storage Junction Temperature
Thermal Resistance
FEATURES:
•
Device is
Halogen Free
by design
•
Low rDS(ON)
•
MAX Threshold Voltage (0.85V)
•
Logic level compatibility
SYMBOL
VDS
VGS
ID
ID
IS
IDM
ISM
PD
PD
PD
TJ, Tstg
Θ
JA
UNITS
V
V
mA
mA
mA
A
A
mW
mW
mW
°C
°C/W
20
8.0
860
950
360
4.0
4.0
350
300
150
-65 to +150
357
ELECTRICAL CHARACTERISTICS:
(TA=25°C unless otherwise noted)
SYMBOL
TEST CONDITIONS
MIN
TYP
IGSSF, IGSSR
VGS=8.0V, VDS=0
1.0
IDSS
VDS=20V, VGS=0
5.0
BVDSS
VGS=0, ID=250μA
20
24
VGS(th)
VDS=VGS, ID=250μA
0.45
VSD
VGS=0 IS=360mA
rDS(ON)
VGS=4.5V, ID=0.95A
0.085
rDS(ON)
rDS(ON)
rDS(ON)
rDS(ON)
VGS=4.5V, ID=0.77A
VGS=2.5V, ID=0.67A
VGS=1.8V, ID=0.20A
VGS=1.2V, ID=0.10A
0.085
0.13
0.19
0.60
MAX
50
500
0.85
0.9
0.15
0.142
0.20
0.24
UNITS
nA
nA
V
V
V
Ω
Ω
Ω
Ω
Ω
Notes: (1) Ceramic or aluminum core PC Board with copper mounting pad area of 4.0mm
2
(2) FR-4 Epoxy PC Board with copper mounting pad area of 4.0mm
2
(3) FR-4 Epoxy PC Board with copper mounting pad area of 1.4mm
2
R2 (2-August 2011)
CMLDM8120TG
SURFACE MOUNT
P-CHANNEL
ENHANCEMENT-MODE
SILICON MOSFET
ELECTRICAL
SYMBOL
Qg(tot)
Qgs
Qgd
gFS
Crss
Ciss
Coss
ton
toff
CHARACTERISTICS - Continued:
(TA=25°C unless otherwise noted)
TEST CONDITIONS
MIN
TYP
MAX
VDS=10V, VGS=4.5V, ID=1.0A
3.56
VDS=10V, VGS=4.5V, ID=1.0A
0.36
VDS=10V, VGS=4.5V, ID=1.0A
VDS=10V, ID=0.81A
VDS=16V, VGS=0, f=1.0MHz
VDS=16V, VGS=0, f=1.0MHz
VDS=16V, VGS=0, f=1.0MHz
VDD=10V, VGS=4.5V, ID=0.95A, RG=6Ω
VDD=10V, VGS=4.5V, ID=0.95A, RG=6Ω
1.52
2.0
80
200
60
20
25
UNITS
nC
nC
nC
S
pF
pF
pF
ns
ns
SOT-563 CASE - MECHANICAL OUTLINE
PIN CONFIGURATION
LEAD CODE:
1) Drain
2) Drain
3) Gate
4) Source
5) Drain
6) Drain
MARKING CODE: CT8
R2 (2-August 2011)
w w w. c e n t r a l s e m i . c o m