TM
82C84A
CMOS Clock Generator Driver
Description
The Intersil 82C84A is a high performance CMOS Clock Generator-
driver which is designed to service the requirements of both CMOS
and NMOS microprocessors such as the 80C86, 80C88, 8086 and
the 8088. The chip contains a crystal controlled oscillator, a divide-by-
three counter and complete “Ready” synchronization and reset logic.
Static CMOS circuit design permits operation with an external fre-
quency source from DC to 25MHz. Crystal controlled operation to
25MHz is guaranteed with the use of a parallel, fundamental mode
crystal and two small load capacitors.
All inputs (except X1 and RES) are TTL compatible over tempera-
ture and voltage ranges.
Power consumption is a fraction of that of the equivalent bipolar cir-
cuits. This speed-power characteristic of CMOS permits the
designer to custom tailor his system design with respect to power
and/or speed requirements.
March 1997
Features
• Generates the System Clock For CMOS or NMOS
Microprocessors
• Up to 25MHz Operation
• Uses a Parallel Mode Crystal Circuit or External
Frequency Source
• Provides Ready Synchronization
• Generates System Reset Output From Schmitt Trigger
Input
• TTL Compatible Inputs/Outputs
• Very Low Power Consumption
• Single 5V Power Supply
• Operating Temperature Ranges
- C82C84A . . . . . . . . . . . . . . . . . . . . . . . . . 0
o
C to +70
o
C
- I82C84A . . . . . . . . . . . . . . . . . . . . . . . . -40
o
C to +85
o
C
- M82C84A . . . . . . . . . . . . . . . . . . . . . . -55
o
C to +125
o
C
Ordering Information
PART
NUMBER
CP82C84A
IP82C84A
CS82C84A
IS82C84A
CD82C84A
ID82C84A
MD82C84A/B
8406801VA
MR82C84A/B
84068012A
-55
o
C to +125
o
C
TEMP. RANGE
0
o
C to +70
o
C
-40
o
C to +85
o
C
0
o
C to +70
o
C
-40
o
C to +85
o
C
0
o
C to +70
o
C
-40
o
C to +85
o
C
-55
o
C to +125
o
C
SMD#
20 Pad CLCC
SMD#
PACKAGE
18 Ld PDIP
20 Ld PLCC
PKG.
NO.
E18.3
E18.3
N20.35
N20.35
18 Ld CERDIP F18.3
F18.3
F18.3
F18.3
J20.A
J20.A
Pinouts
82C84A (PDIP, CERDIP)
TOP VIEW
CSYNC
PCLK
AEN1
RDY1
READY
RDY2
AEN2
CLK
GND
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
V
CC
X1
X2
RDY1
ASYNC
READY
EFI
F/C
OSC
RES
RESET
RDY2
AEN2
NC
4
5
6
7
8
9
CLK
10
GND
11
RESET
12
RES
13
OSC
82C84A (PLCC, CLCC)
TOP VIEW
CSYNC
PCLK
AEN1
V
CC
20
3
2
1
19
18
17
16
15
14
X2
ASYNC
EFI
F/C
NC
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
X1
FN2974.1
287
82C84A
Functional Diagram
11
RES
X1
X2
17
16
XTAL
OSCILLATOR
D
CK
Q
10
RESET
12
OSC
F/C
EF1
CSYNC
RDY1
AEN1
RDY2
AEN2
ASYNC
13
14
1
4
3
6
7
15
CK
D
Q
FF1
÷
3
SYNC
÷
2
SYNC
2
PCLK
8
CLK
CK
5
D
Q
FF2
READY
CONTROL PIN
F/C
RES
RDY1, RDY2
AEN1, AEN2
ASYNC
LOGICAL 1
External Clock
Normal
Bus Ready
Address Disabled
1 Stage Ready
Synchronization
LOGICAL 0
Crystal Drive
Reset
Bus Not Ready
Address Enable
2 Stage Ready
Synchronization
288
82C84A
Pin Description
SYMBOL
AEN1,
AEN2
NUMBER
3, 7
TYPE
I
DESCRIPTION
ADDRESS ENABLE: AEN is an active LOW signal. AEN serves to qualify its respective Bus
Ready Signal (RDY1 or RDY2). AEN1 validates RDY1 while AEN2 validates RDY2. Two AEN
signal inputs are useful in system configurations which permit the processor to access two Multi-
Master System Busses. In non-Multi-Master configurations, the AEN signal inputs are tied true
(LOW).
BUS READY (Transfer Complete). RDY is an active HIGH signal which is an indication from a
device located on the system data bus that data has been received, or is available RDY1 is qual-
ified by AEN1 while RDY2 is qualified by AEN2.
READY SYNCHRONIZATION SELECT: ASYNC is an input which defines the synchronization
mode of the READY logic. When ASYNC is low, two stages of READY synchronization are pro-
vided. When ASYNC is left open or HIGH, a single stage of READY synchronization is provided.
READY: READY is an active HIGH signal which is the synchronized RDY signal input. READY
is cleared after the guaranteed hold time to the processor has been met.
CRYSTAL IN: X1 and X2 are the pins to which a crystal is attached. The crystal frequency is 3
times the desired processor clock frequency, (Note 1).
FREQUENCY/CRYSTAL SELECT: F/C is a strapping option. When strapped LOW. F/C permits
the processor’s clock to be generated by the crystal. When F/C is strapped HIGH, CLK is gener-
ated for the EFI input, (Note 1).
EXTERNAL FREQUENCY IN: When F/C is strapped HIGH, CLK is generated from the input fre-
quency appearing on this pin. The input signal is a square wave 3 times the frequency of the de-
sired CLK output.
PROCESSOR CLOCK: CLK is the clock output used by the processor and all devices which di-
rectly connect to the processor’s local bus. CLK has an output frequency which is 1/3 of the crys-
tal or EFI input frequency and a 1/3 duty cycle.
PERIPHERAL CLOCK: PCLK is a peripheral clock signal whose output frequency is 1/2 that of
CLK and has a 50% duty cycle.
OSCILLATOR OUTPUT: OSC is the output of the internal oscillator circuitry. Its frequency is
equal to that of the crystal.
RESET IN: RES is an active LOW signal which is used to generate RESET. The 82C84A pro-
vides a Schmitt trigger input so that an RC connection can be used to establish the power-up
reset of proper duration.
RESET: RESET is an active HIGH signal which is used to reset the 80C86 family processors. Its
timing characteristics are determined by RES.
CLOCK SYNCHRONIZATION: CSYNC is an active HIGH signal which allows multiple 82C84As
to be synchronized to provide clocks that are in phase. When CSYNC is HIGH the internal
counters are reset. When CSYNC goes LOW the internal counters are allowed to resume count-
ing. CSYNC needs to be externally synchronized to EFI. When using the internal oscillator
CSYNC should be hardwired to ground.
Ground
V
CC
: The +5V power supply pin. A 0.1µF capacitor between V
CC
and GND is recommended for
decoupling.
RDY1,
RDY2
4, 6
I
ASYNC
15
I
READY
5
O
X1, X2
17, 16
IO
F/C
13
I
EFI
14
I
CLK
8
O
PCLK
2
O
OSC
12
O
RES
11
I
RESET
10
O
CSYNC
1
I
GND
V
CC
NOTE:
9
18
1. If the crystal inputs are not used X1 must be tied to V
CC
or GND and X2 should be left open.
289
82C84A
Functional Description
Oscillator
The oscillator circuit of the 82C84A is designed primarily for
use with an external parallel resonant, fundamental mode
crystal from which the basic operating frequency is derived.
The crystal frequency should be selected at three times the
required CPU clock. X1 and X2 are the two crystal input
crystal connections. For the most stable operation of the
oscillator (OSC) output circuit, two capacitors (C1 = C2) as
shown in the waveform figures are recommended. The out-
put of the oscillator is buffered and brought out on OSC so
that other system timing signals can be derived from this sta-
ble, crystal-controlled source.
TABLE 1. CRYSTAL SPECIFICATIONS
PARAMETER
Frequency
Type of Operation
Unwanted Modes
Load Capacitance
TYPICAL CRYSTAL SPEC
2.4 - 25MHz, Fundamental, “AT” cut
Parallel
6dB (Minimum)
18 - 32pF
Clock Outputs
The CLK output is a 33% duty cycle clock driver designed to
drive the 80C86, 80C88 processors directly. PCLK is a periph-
eral clock signal whose output frequency is 1/2 that of CLK.
PCLK has a 50% duty cycle.
Reset Logic
The reset logic provides a Schmitt trigger input (RES) and a
synchronizing flip-flop to generate the reset timing. The reset
signal is synchronized to the falling edge of CLK. A simple RC
network can be used to provide power-on reset by utilizing this
function of the 82C84A.
READY Synchronization
Two READY input (RDY1, RDY2) are provided to accommo-
date two system busses. Each input has a qualifier (AEN1 and
AEN2, respectively). The AEN signals validate their respective
RDY signals. If a Multi-Master system is not being used the
AEN pin should be tied LOW.
Synchronization is required for all asynchronous active-going
edges of either RDY input to guarantee that the RDY setup
and hold times are met. Inactive-going edges of RDY in nor-
mally ready systems do not require synchronization but must
satisfy RDY setup and hold as a matter of proper system
design.
The ASYNC input defines two modes of READY synchroniza-
tion operation.
When ASYNC is LOW, two stages of synchronization are pro-
vided for active READY input signals. Positive-going asyn-
chronous READY inputs will first be synchronized to flip-flop
one of the rising edge of CLK (requiring a setup time tR1VCH)
and the synchronized to flip-flop two at the next falling edge of
CLK, after which time the READY output will go active (HIGH).
Negative-going asynchronous READY inputs will be synchro-
nized directly to flip-flop two at the falling edge of CLK, after
which the READY output will go inactive. This mode of opera-
tion is intended for use by asynchronous (normally not ready)
devices in the system which cannot be guaranteed by design
to meet the required RDY setup timing, TR1VCL, on each bus
cycle.
When ASYNC is high or left open, the first READY flip-flop is
bypassed in the READY synchronization logic. READY inputs
are synchronized by flip-flop two on the falling edge of CLK
before they are presented to the processor. This mode is
available for synchronous devices that can be guaranteed to
meet the required RDY setup time.
ASYNC can be changed on every bus cycle to select the
appropriate mode of synchronization for each device in the
system.
Capacitors C1, C2 are chosen such that their combined
capacitance
C1 x C2
-
CT =
---------------------
(Including stray capacitance)
C1 + C2
matches the load capacitance as specified by the crystal
manufacturer. This ensures operation within the frequency
tolerance specified by the crystal manufacturer.
Clock Generator
The clock generator consists of a synchronous divide-by-
three counter with a special clear input that inhibits the
counting. This clear input (CSYNC) allows the output clock
to be synchronized with an external event (such as another
82C84A clock). It is necessary to synchronize the CSYNC
input to the EFI clock external to the 82C84A. This is accom-
plished with two flip-flops. (See Figure 1). The counter out-
put is a 33% duty cycle clock at one-third the input
frequency.
NOTE: The F/C input is a strapping pin that selects either the crystal
oscillator or the EFI input as the clock for the
÷
3 counter. If
the EFI input is selected as the clock source, the oscillator
section can be used independently for another clock source.
Output is taken from OSC.
EFI
CLOCK
SYNCHRONIZE
EFI
D
Q
D
Q
82C84A
CSYNC
>
>
(TO OTHER 82C84As)
NOTE: If EFI input is used, then crystal input X1 must be tied to V
CC
or GND and X2 should be left open. If the crystal inputs are used,
then EFI should be tied to V
CC
or GND.
FIGURE 1. CSYNC SYNCHRONIZATION
290
82C84A
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V
Input, Output or I/O Voltage . . . . . . . . . . . GND -0.5V to V
CC
+0.5V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Information
Thermal Resistance . . . . . . . . . . . . . . . .
θ
JA
(
o
C/W)
θ
JC
(
o
C/W)
CERDIP Package . . . . . . . . . . . . . . . .
80
20
CLCC Package . . . . . . . . . . . . . . . . . .
95
28
PDIP Package . . . . . . . . . . . . . . . . . . .
85
N/A
PLCC Package . . . . . . . . . . . . . . . . . .
85
N/A
Storage Temperature Range . . . . . . . . . . . . . . . . .-65
o
C to +150
o
C
Max Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +175
o
C
Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300
o
C
(PLCC - Lead Tips Only)
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Range
C82C84A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0
o
C to +70
o
C
I82C84A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40
o
C to +85
o
C
M82C84A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55
o
C to +125
o
C
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
DC Electrical Specifications
V
CC
= +5.0V
±10%,
T
A
= 0
o
C to +70
o
C (C82C84A),
T
A
= -40
o
C to +85
o
C (I82C84A),
T
A
= -55
o
C to +125
o
C (M82C84A)
SYMBOL
V
IH
V
IL
V
IHR
V
ILR
VT+ - VT-
V
OH
V
OL
II
PARAMETER
Logical One Input Voltage
MIN
2.0
2.2
-
V
CC
-0.8
-
0.2 V
CC
V
CC
-0.4
-
MAX
-
UNITS
V
V
V
V
V
-
V
I
OH
= -4.0mA for CLK Output
I
OH
= -2.5mA for All Others
I
OL
= +4.0mA for CLK Output
I
OL
= +2.5mA for All Others
V
IN
= V
CC
or GND except ASYNC,
X1: (Note 4)
Crystal Frequency = 25MHz
Outputs Open, Note 5
TEST CONDITIONS
C82C84A, I82C84
M82C84A, Notes 1, 2
Notes 1, 2, 3
Logical Zero Input Voltage
Reset Input High Voltage
Reset Input Low Voltage
Reset Input Hysteresis
Logical One Output Current
0.8
-
0.5
-
-
Logical Zero Output Voltage
0.4
V
µA
Input Leakage Current
-1.0
1.0
I
CCOP
NOTES:
Operating Power Supply Current
-
40
mA
1. F/C is a strap option and should be held either
≤
0.8V or
≥
2.2V. Does not apply to X1 or X2 pins.
2. Due to test equipment limitations related to noise, the actual tested value may differ from that specified, but the specified limit is
guaranteed.
3. CSYNC pin is tested with V
IL
≤
0.8V.
4. ASYNC pin includes an internal 17.5kΩ nominal pull-up resistor. For ASYNC input at GND, ASYNC input leakage current = 300µA
nominal, X1 - crystal feedback input.
5. f = 25MHz may be tested using the extrapolated value based on measurements taken at f = 2MHz and f = 10MHz.
Capacitance
T
A
= +25
o
C
SYMBOL
C
IN
C
OUT
PARAMETER
Input Capacitance
Output Capacitance
TYPICAL
10
15
UNITS
pF
pF
TEST CONDITIONS
FREQ = 1MHz, all measurements are
referenced to device GND
291
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
