CY2276A-21
CY2276A-31
Pentium®/II Clock Synthesizer/Driver for Desktop PCs
with Intel 82440LX and 3–4 DIMMs
Features
• Mixed 2.5V and 3.3V operation
• Single-chip clock solution to meet requirements of Pen-
tium® and Pentium® II motherboards
— Multiple CPU clocks at 2.5V supporting single and
dual-processor systems
— Seven synchronous PCI clocks
— Multiple 2.5V IOAPIC clocks at 14.318 MHz
— Multiple 3.3V SDRAM clocks
— Multiple 3.3V USB and I/O clocks
— Multiple 3.3V Ref. clocks at 14.318 MHz
• I
2
C™ Serial Configuration Interface
• Factory-EPROM programmable output drive and slew
rate for EMI customization
• Factory-EPROM programmable clock frequencies for
custom configurations
• High drive, low skew, and low jitter outputs
• Available in space-saving 56-pin SSOP package
outputs available from each device, as shown in the Selector
Guide.
The CY2276A-21 is ideal for four-SDRAM module or server
applications that require sixteen SDRAM clocks, and do not
require the ability to stop CPU clocks. The CY2276A-31 is ide-
al for single-processor or dual-processor desktop systems,
which require an extra CPU clock.
All CY2276A outputs are designed for low EMI emissions.
Controlled rise and fall times, unique output driver circuits and
factory-EPROM programmable output drive and slew-rate en-
able optimal configurations for EMI control.
CY2276A Selector Guide.
Clock Outputs
CPU (60, 66.6 MHz)
SDRAM
PCI (CPU/2 MHz)
IOAPIC (14.318 MHz)
USB/IO (48 MHz)
IO (24 MHz)
Ref. (14.318 MHz)
CPU-PCI delay
-21
4
16
7
2
1
1
1
1–6 ns
-31
5
13
7
2
2
0
2
1–5 ns
Functional Description
The CY2276A-21 andCY2276A-31 are single-chip clock gen-
erators for Pentium or Pentium II systems designed with the
Intel® 82440LX or similar chipset. They differ in the number of
Logic Block Diagram
OE
IOAPIC (14.318 MHz)
V
DDQ2
XTALIN
XTALOUT
REF (14.318 MHz)
14.318
MHz
OSC.
CPU
PLL
CPUCLK
V
DDCPU
SDRAM
Available on -31 only
SEL
EPROM
/2
EPROM
Prog.
Delay
PCI [0–6]
SYS
PLL
/2
USBCLK (48 MHz)
IOCLK (24 MHz)
SCLK
SDATA
SERIAL
INTERFACE
CONTROL
LOGIC
Please refer to Selector Guide for exact number of outputs on each device
Intel and Pentium are registered trademarks of Intel Corporation.
I
2
C is a trademark of Philips Corporation.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
October 12, 1998
CY2276A-21
CY2276A-31
Pin Configurations
56 SSOP
Top View
AV
DD
IOCLK
USBCLK
V
SS
XTALIN
XTALOUT
REF0
V
DDQ3
PCICLK6
PCICLK0
V
SS
PCICLK1
PCICLK2
PCICLK3
PCICLK4
V
DDQ3
PCICLK5
V
SS
SDRAM11
SDRAM10
V
DDQ3
SDRAM9
SDRAM8
V
SS
SDRAM15
SDRAM14
V
DDQ3
SDATA
1
2
3
4
5
6
7
8
9
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
V
DDQ2
IOAPIC0
IOAPIC1
V
SS
CPUCLK0
CPUCLK1
V
DDCPU
CPUCLK2
CPUCLK3
V
SS
SDRAM0
SDRAM1
V
DDQ3
SDRAM2
SDRAM3
V
SS
SDRAM4
SDRAM5
V
DDQ3
SDRAM6
SDRAM7
V
SS
SDRAM12
SDRAM13
V
SS
OE
MODE
SCLK
AV
DD
REF0
REF1
V
SS
XTALIN
XTALOUT
V
DDQ3
PCICLK6
PCICLK0
V
SS
PCICLK1
PCICLK2
PCICLK3
PCICLK4
V
DDQ3
PCICLK5
V
SS
USBCLK0
USBCLK1
V
DDQ3
N/C
SDRAM12
V
SS
SDRAM11
SDRAM10
V
DDQ3
SDATA
SCLK
1
2
3
4
5
6
7
8
9
56 SSOP
Top View
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
V
DDQ2
IOAPIC0
IOAPIC1
V
SS
CPUCLK0
CPUCLK1
V
DDCPU
CPUCLK2
CPUCLK3
V
SS
CPUCLK4
SDRAM0
SDRAM1
V
DDQ3
SDRAM2
SDRAM3
V
SS
SDRAM4
SDRAM5
V
DDQ3
SDRAM6
SDRAM7
V
SS
SDRAM8
SDRAM9
V
SS
SEL
OE
CY2276A-21
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
2
CY2276A-31
10
10
CY2276A-21
CY2276A-31
Pin Summary
Name
V
DDQ3
V
DDQ2
V
DDCPU
AV
DD
V
SS
XTALIN
[1]
XTALOUT
[1]
SDRAM[0–15]
(-21)
SDRAM[0–12]
(-31)
Pins (-21)
8, 16, 21, 27,
38, 44
56
50
1
4, 11, 18, 24,
32, 35, 41, 47,
53
5
6
46, 45, 43, 42,
40, 39, 37, 36,
23, 22, 20, 19,
34, 33, 26, 25
31
52, 51, 49, 48
10, 12, 13, 14,
15, 17, 9
55, 54
7
3
2
28
29
N/A
30
N/A
N/A
Pins (-31)
7, 15, 20, 26,
37, 43
56
50
1
4, 10, 17, 23,
31, 34, 40, 47,
53
5
6
45, 44, 42, 41,
39, 38, 36, 35,
33, 32, 25, 24,
22
29
52, 51, 49, 48,
46
9, 11, 12, 13,
14, 16, 8
55, 54
2, 3
18, 19
N/A
27
28
N/A
N/A
21
30
Description
3.3V Digital voltage supply
IOAPIC Digital voltage supply, 2.5V
CPU Digital voltage supply, 2.5V
Analog voltage supply, 3.3V
Ground
Reference crystal input
Reference crystal feedback
SDRAM clock outputs
OE
CPUCLK [0–3]
(-21)
CPUCLK [0–4]
(-31)
PCICLK [0–6]
(All)
IOAPIC [0–1]
(All)
REF0
(-21)
REF [0–1]
(-31)
USBCLK
(-21)
USBCLK [0–1]
(-31)
IOCLK
SDATA
SCLK
CPU_STOP
MODE
N/C
SEL
Active HIGH output enable, disables all outputs when asserted
CPU clock outputs
PCI clock outputs, running at one-half the CPU frequency
IOAPIC clock outputs
Reference clock outputs, 14.318 MHz. REF0 drives 45 pF load
48 MHz USB clock output
24 MHz I/O clock output
Serial data input for serial configuration port
Serial clock input for serial configuration port
Active LOW input, disables CPU clocks when asserted
Mode input, not used, tie to V
SS
Not connected. Tie to V
SS
CPU frequency select input (see Function Table)
Note:
1. For best accuracy, use a parallel-resonant crystal, C
LOAD
= 18 pF.
3
CY2276A-21
CY2276A-31
Function Table
Device
-21
-21
-31
-31
-31
0
1
0
1
1
OE
SEL
N/A
N/A
X
0
1
XTALIN
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
CPUCLK
SDRAM
Hi-Z
66.67 MHz
Hi-Z
60 MHz
66.67 MHz
PCICLK
Hi-Z
33.33 MHz
Hi-Z
30 MHz
33.33 MHz
REF
IOAPIC
Hi-Z
14.318 MHz
Hi-Z
14.318 MHz
14.318 MHz
Hi-Z
48 MHz
Hi-Z
48 MHz
48 MHz
USB
I/O
(-21 only)
Hi-Z
24 MHz
N/A
N/A
N/A
Actual Clock Frequency Values
Clock Output
CPUCLK
CPUCLK
Target
Frequency
(MHz)
66.67
60.0
Actual
Frequency
(MHz)
66.654
60.0
0
PPM
–195
CPU and PCI Clock Driver Strengths
• Matched impedances on both rising and falling edges on
the output drivers
• Output impedance: 25Ω (typical) measured at 1.5V.
Byte 0: Functional and Frequency Select Clock
Register (1 = Enable, 0 = Disable)
Bit
Pin #
Description
(Reserved) drive to ‘0’
(Reserved) drive to ‘0’
(Reserved) drive to ‘0’
(Reserved) drive to ‘0’
(Reserved) drive to ‘0’
(Reserved) drive to ‘0’
Bit 1
1
1
0
0
Bit 0
1 - N/A
0 - N/A
1 - Testmode
0 - Normal Operation
Bit 7 --
Bit 6 --
Bit 5 --
Bit 4 --
Bit 3 --
Bit 2 --
Bit 1 --
Bit 0
Serial Configuration Map
• The Serial bits will be read by the clock driver in the following
order:
Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0
.
.
Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0
• Reserved and unused bits should be programmed to “0”.
• I
2
C Address for the CY2276A-21,-31 is:
A6
1
A5
1
A4
0
A3
1
A2
0
A1
0
A0
1
R/W
----
Select Functions
Outputs
Functional Description
Test Mode
CPU
TCLK/2
[2]
PCI, PCI_F
TCLK/4
SDRAM
TCLK/2
Ref
TCLK
IOAPIC
TCLK
Note:
2. TCLK supplied on the XTALIN pin in Test Mode.
4
CY2276A-21
CY2276A-31
Byte 1: CPU Active/Inactive Register
(1 = Active, 0 = Inactive), Default = Active
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Description
IOCLK (Active/Inactive) (-21 ONLY)
USBCLK0 (Active/Inactive) (-31 ONLY)
USBCLK (Active/Inactive) (-21 ONLY)
USBCLK1 (Active/Inactive) (-31 ONLY)
(Reserved) drive to ‘0’
CPUCLK4 (Active/Inactive) (-31 ONLY)
Not available on -21
CPUCLK3 (Active/Inactive)
CPUCLK2 (Active/Inactive)
CPUCLK1 (Active/Inactive)
CPUCLK0 (Active/Inactive)
Byte 2: PCI Active/Inactive Register
(1 = Active, 0 = Inactive), Default = Active
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Description
(Reserved) drive to ‘0’
PCICLK6 (Active/Inactive)
PCICLK5 (Active/Inactive)
PCICLK4 (Active/Inactive)
PCICLK3 (Active/Inactive)
PCICLK2 (Active/Inactive)
PCICLK1 (Active/Inactive)
PCICLK0 (Active/Inactive)
Byte 4: SDRAM Active/Inactive Register
(1 = Active, 0 = Inactive), Default = Active
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Description
SDRAM15 (Active/Inactive) (-21 ONLY)
Not available on -31
SDRAM14 (Active/Inactive) (-21 ONLY)
Not available on -31
SDRAM13 (Active/Inactive) (-21 ONLY)
Not available on -31
SDRAM12 (Active/Inactive)
SDRAM11 (Active/Inactive)
SDRAM10 (Active/Inactive)
SDRAM9 (Active/Inactive)
SDRAM8 (Active/Inactive)
Byte 3: SDRAM Active/Inactive Register
(1 = Active, 0 = Inactive), Default = Active
Bit
Description
Bit 7 SDRAM7 (Active/Inactive)
Bit 6 SDRAM6 (Active/Inactive)
Bit 5 SDRAM5 (Active/Inactive)
Bit 4 SDRAM4 (Active/Inactive)
Bit 3 SDRAM3 (Active/Inactive)
Bit 2 SDRAM2 (Active/Inactive)
Bit 1 SDRAM1 (Active/Inactive)
Bit 0 SDRAM0 (Active/Inactive)
Byte 5: Peripheral Active/Inactive Register
(1 = Active, 0 = Inactive), Default = Active
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Description
(Reserved drive to ‘0’)
(Reserved) drive to ‘0’
IOAPIC1 (Active/Inactive)
IOAPIC0 (Active/Inactive)
(Reserved) drive to ‘0’
(Reserved) drive to ‘0’
REF1 (Active/Inactive)(-31 ONLY)
REF0 (Active/Inactive)
Byte 6: Reserved, for future use
5
51单片机
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