USBCLK long term jitter:........................................... ±500 ps
Table 2. Spread Characteristics
SSON#
0
0
0
0
1
1
1
1
SS%1
0
0
1
1
0
0
1
1
SS%0
0
1
0
1
0
1
0
1
CPU(0:3),
SDRAM(0:11)
–0.5%
–1.0%
–2.5%
–3.75%
0 (off)
0 (off)
0 (off)
0 (off)
Block Diagram
X1
X2
XTAL
OSC
PLL Ref Freq
SSON#
SS%1
SS%0
REF
Pin Configuration
[2, 3]
GND
VDDCORE
VDDCORE
REF
GND
X1
X2
GND
SDRAM11
SDRAM10
VDDS
SDRAM9
SDRAM8
GND
SDRAM7
SDRAM6
VDDS
SDRAM5
SDRAM4
GND
VDDCORE
*SD4EN
*SD8EN
*SS%0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
USBCLKEN
GND
USBCLK
VDDU
VDDCORE
GND
GND
CPU0
CPU1
VDDC
CPU2
CPU3
GND
SDRAM0
SDRAM1
VDDS
SDRAM2
SDRAM3
GND
VDDS
SS%1*
SSON#^
FS1*
FS0*
CPU0:3
SDRAM0:3
PLL 1
SDRAM4:7
SDRAM8:11
FS0
FS1
SD4EN
SD8EN
USBCLKEN
PLL 2
USBCLK
Notes:
1. All clock output loaded with maximum lump capacitance test load specified in AC Electrical Characteristics section.
2. Signals marked with [*] have internal pull-up resistors.
3. Signals marked with [^] have internal pull-down resistors.
Cypress Semiconductor Corporation
Document #: 38-07346 Rev. **
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised January 22, 2002
CY24246
Pin Definitions
Pin Name
CPU0:3
Pin
No.
41,40,38,37
Pin
Type
O
Pin Description
CPU Clock Outputs:
These four outputs run at a frequency set by FS0:1. The
width of the Spread Spectrum Modulation is enabled by pin SSON#, and
selected by pins SS%0:1.
SDRAM Outputs:
These twelve SDRAM clock outputs run synchronously to the
CPU clock. Modulation and frequency follow the CPU outputs.
SDRAM0:11
35, 34, 32,
31, 19, 18,
16, 15, 13,
12, 10, 9
25, 26
24, 28
46
O
FS0:1
SS%0:1
USBCLK
I
I
O
Frequency Selection Inputs:
Selects CPU clock frequency as shown in
Table 1.
Modulation Width Selection Inputs:
These inputs select the width of the
Spread Spectrum feature when it is enabled by SSON#. See
Table 2.
USB Output:
Timing signal running at 48.0080 MHz when a 14.31818-MHz
frequency is provided as the reference. (167-ppm accuracy to 48 MHz, the
output is equal to the reference times 57/17.)
CPU Spread Spectrum Enable Input:
When this pin is pulled LOW, outputs
CPU0:3 and SDRAM0:11 will have the Spread Spectrum Feature enabled.
USB Disable Input:
When this pin is pulled LOW, output USBCLK will be
disabled to a LOW state.
Reference output:
This output will be equal in frequency to the reference signal
provided at X1/X2.
SDRAM Bank Disable Input:
When this pin is pulled LOW, outputs SDRAM4:7
will be disabled to a LOW state.
SDRAM Bank Disable Input:
When this pin is pulled LOW, outputs SDRAM8:11
will be disabled to a LOW state.
Crystal Connection or External Reference Frequency Input:
Connect to
either a 14.318-MHz crystal or other reference signal.
Crystal Connection:
An input connection for an external 14.318-MHz crystal.
If using an external reference, this pin must be left unconnected.
Power Connection:
Core Power supply. Connect to 3.3V supply.
Power Connection:
Power supply for the USB output. Connect to 3.3V or 2.5V
supply.
Power Connection:
Power supply for the CPU outputs. Connect to 2.5V supply.
Power Connection:
Power supply for the SDRAM outputs. Connect to 3.3V
supply.
Ground Connections:
Connect all ground pins to the common system ground
plane.
SSON#
USBCLKEN
REF
SD4EN
SD8EN
X1
X2
VDDCORE
VDDU
VDDC
VDDS
GND
27
48
4
22
23
6
7
2, 3, 21, 44
45
39
11, 17, 29, 33
1, 5, 8, 14, 20,
30, 36, 42,
43, 47
I
I
O
I
I
I
I
P
P
P
P
G
Document #: 38-07346 Rev. **
Page 2 of 9
CY24246
Spread Spectrum Generator
The device generates a clock that is frequency modulated in
order to increase the bandwidth that it occupies. By increasing
the bandwidth of the fundamental and its harmonics, the
amplitudes of the radiated electromagnetic emissions are
reduced. This effect is depicted in
Figure 1.
As depicted in
Figure 1,
a harmonic of a modulated clock has
a much lower amplitude than that of an unmodulated signal.
The reduction in amplitude is dependent on the harmonic
number and the frequency deviation or spread. The equation
for the reduction is
dB = 6.5 + 9*log
10
(P) + 9*log
10
(F)
where
P
is the percentage of deviation and
F
is the frequency
in MHz at which the reduction is measured.
EMI Reduction
The output clock is modulated with a waveform depicted in
Figure 2.
This waveform, as discussed in “Spread Spectrum
Clock Generation for the Reduction of Radiated Emissions” by
Bush, Fessler, and Hardin, produces the maximum reduction
in the amplitude of radiated electromagnetic emissions. The
deviation selected for this chip is ±0.5% of the center
frequency.
Figure 2
details the Cypress spreading pattern.
Cypress does offer options with more spread and greater EMI
reduction. Contact your local Sales representative for details
on these devices.
Spread Spectrum clocking is activated or deactivated by
selecting the appropriate values for bits 1–0 in data byte 0 of
the SMBus data stream.
Spread
Spectrum
Enabled
Non-
Spread
Spectrum
-SS%
Frequency Span (MHz)
Figure 1. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation
MAX (+.0.5%)
FREQUENCY
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
10%
20%
30%
40%
50%
60%
70%
80%
90%
MIN. (–0.5%)
Figure 2. Typical Modulation Profile
Document #: 38-07346 Rev. **
100%
Page 3 of 9
CY24246
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause
permanent damage to the device. These represent a stress
Parameter
V
DD
, V
IN
T
STG
T
A
T
B
ESD
PROT
Description
Voltage on Any Pin with Respect to GND
Storage Temperature
Operating Temperature
Ambient Temperature under Bias
Input ESD Protection
rating only. Operation of the device at these or any other condi-
tions above those specified in the operating sections of this
specification is not implied. Maximum conditions for extended
periods may affect reliability.
Rating
–0.5 to +7.0
–65 to +150
–55 to +125
0 to +70
2 (min.)
Unit
V
°C
°C
°C
kV
DC Electrical Characteristics:
T
A
= 0°C to +70°C, V
DDS
= 3.3V ± 10%, V
DD_CORE
= 3.3V ± 10%, V
DDU
= 3.3V ± 10%, V
DDC
= 2.5V ± 5%
Parameter
Supply Current
I
DD3
I
DD2
Logic Inputs
V
IL
V
IH
I
IL
I
IH
V
TH
C
LOAD
C
IN,X1
C
IN
C
OUT
L
IN
V
OL
V
OH
I
OL
I
OH
V
OL
V
OH
I
OL
I
OH
Input LOW Voltage
Input HIGH Voltage
Input LOW Current
[5]
Description
Supply Current (3.3V)
Supply Current (2.5V)
Test Condition
CPUCLK =100 MHz
Outputs Loaded
[4]
CPUCLK =100 MHz
Outputs Loaded
[4]
Min.
Typ.
Max.
350
75
Unit
mA
mA
GND – 0.3
2.0
0.8
VDD + 0.3
–25
10
1.5
14
V
V
µA
µA
V
pF
pF
Input HIGH Current
[5]
X1 Input Threshold Voltage
[1]
Load Capacitance, Imposed on
External Crystal
[6]
X1 Input Capacitance
[7]
Input Pin Capacitance
Output Pin Capacitance
Input Pin Inductance
Output LOW Voltage
Output HIGH Voltage
Output LOW Current
[5]
Output HIGH Current
[5]
Output LOW Voltage
Output HIGH Voltage
Output LOW Current
[5]
Crystal Oscillator
Pin X2 unconnected
Except X1 and X2
28
5
6
7
Pin Capacitance/Inductance
pF
pF
nH
mV
V
75
75
50
3.1
100
100
mA
mA
mV
V
mA
mA
CPU Outputs
I
OL
= 1mA
I
OH
= -1mA
V
OL
= 1.25V
V
OH
= 1.25V
I
OL
= 1mA
I
OH
= –1mA
V
OL
= 1.50V
V
OH
= 1.50V
2.0
50
48 MHz/USBCLK Outputs
Output HIGH Current
[5]
Notes:
4. CY24246 logic inputs have internal pull-up resistors.
5. X1 input threshold voltage (typical) is V
DDQ
/2.
6. The CY24246 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is
14 pF; this includes typical stray capacitance of short PCB traces to crystal.
7. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected).
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