PRELIMINARY
CY2SSTU32866
1.8V, 25-bit (1:1) or 14-bit (1:2)
JEDEC-Compliant Data Register with Parity
Features
• Operating frequency: DC to 500 MHz
• Supports DDRII SDRAM
• Two operations modes: 25 bit (1:1) and 14 bit (1:2)
• 1.8V operation
• Fully JEDEC-compliant (JESD 82-10)
• 96-ball FBGA
CSR# inputs are HIGH. If either DCS# or CSR# input is LOW,
the Qn outputs will function normally. The RESET# input has
priority over the DCS# and CSR# control and will force the
outputs LOW. If the DCS#-control functionality is not desired,
the CSR# input can be hardwired to ground, in which case the
set-up time requirement for DCS# would be the same as for
the other D data inputs.
The device supports low-power standby operation. When the
reset input (RESET#) is LOW, the differential input receivers
are disabled, and undriven (floating) data, clock, and reference
voltage (VREF) inputs are allowed. In addition, when RESET#
is LOW, all registers are reset and all outputs are forced LOW.
The LVCMOS RESET# and Cn inputs must always be held at
a valid logic HIGH or LOW level. To ensure defined outputs
from the register before a stable clock has been supplied,
RESET# must be held in the LOW state during power-up.
In the DDR-II RDIMM application, RESET# is specified to be
completely asynchronous with respect to CK and CK#.
Therefore, no timing relationship can be guaranteed between
the two. When entering reset, the register will be cleared and
the outputs will be driven low quickly, relative to the time to
disable the differential input receivers. However, when coming
out of reset, the register will become active quickly, relative to
the time to enable the differential input receivers.
Functional Description
All clock and data inputs are compatible with the JEDEC
standard for SSTL_18. The control inputs are LVCMOS. All
outputs are 1.8-V CMOS drivers that have been optimized to
drive the DDR-II DIMM load. The CY2SSTU32866 operates
from a differential clock (CK and CK#). Data are registered at
the crossing of CK going high, and CK# going LOW.
The C0 input controls the pinout configuration of the 1:2 pinout
from A configuration (when LOW) to B configuration (when
HIGH). The C1 input controls the pinout configuration from
25-bit 1:1 (when LOW) to 14-bit 1:2 (when HIGH).
The device monitors both DCS# and CSR# inputs and will gate
the Qn outputs from changing states when both DCS# and
Pin Configuration
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
1
DCKE
D2
D3
DODT
D5
D6
PAR_IN
CK
CK#
D8
D9
D10
D11
D12
D13
D14
1
2
PPO
D15
D16
QERR#
D17
D18
RST#
DCS#
CSR#
D19
D20
D21
D22
D23
D24
D25
2
3
VREF
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
VREF
3
4
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
VDD
4
5
QCKE
Q2
Q3
QODT
Q5
Q6
C1
QCS#
ZOH
Q8
Q9
Q10
Q11
Q12
Q13
Q14
5
6
NC
Q15
Q16
NC
Q17
Q18
C0
NC
ZOL
Q19
Q20
Q21
Q22
Q23
Q24
Q25
6
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
1
DCKE
D2
D3
DODT
D5
D6
PAR_IN
CK
CK#
D8
D9
D10
D11
D12
D13
D14
1
2
PPO
NC
NC
QERR#
NC
NC
RST#
DCS#
CSR#
NC
NC
NC
NC
NC
NC
NC
2
3
VREF
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
VREF
3
4
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
VDD
4
5
QCKEA
Q2A
Q3A
QODTA
Q5A
Q6A
C1
QCSA#
ZOH
Q8A
Q9A
Q10A
Q11A
Q12A
Q13A
Q14A
5
6
QCKEB
Q2B
Q3B
QODTB
Q5B
Q6B
C0
QCSB#
ZOL
Q8B
Q9B
Q10B
Q11B
Q12B
Q13B
Q14B
6
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
1
D1
D2
D3
D4
D5
D6
PAR_IN
CK
CK#
D8
D9
D10
DODT
D12
D13
DCKE
1
2
PPO
NC
NC
QERR#
NC
NC
RST#
DCS#
CSR#
NC
NC
NC
NC
NC
NC
NC
2
3
VREF
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
VREF
3
4
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
VDD
4
5
Q1A
Q2A
Q3A
Q4A
Q5A
Q6A
C1
QCSA#
ZOH
Q8A
Q9A
Q10A
QODTA
Q12A
Q13A
QCKEA
5
6
Q1B
Q2B
Q3B
Q4B
Q5B
Q6B
C0
QCSB#
ZOL
Q8B
Q9B
Q10B
QODTB
Q12B
Q13B
QCKEB
6
1:1 Register C0 = 0, C1=0
1:2 Register A C0 = 0, C1=1
1:2 Register B C0 = 1, C1=1
Cypress Semiconductor Corporation
Document #: 38-07690 Rev. **
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Revised December 21, 2004
PRELIMINARY
The CY2SSTV32866 accepts a parity bit from the memory
controller on its parity bit (PAR_IN) input, compares it with the
data received on the DIMM-independent D-inputs and
indicates whether a parity error has occurred on its open-drain
QERR# pin (active LOW). The convention is even parity, i.e.,
valid parity is defined as an even number of ones across the
DIMM-independent data inputs combined with the parity input
bit.
When used as a single device, the C0 and C1 inputs are tied
LOW. In this configuration, parity is checked on the PAR_IN
input which arrives one cycle after the input data to which it
applies. The partial-parity-out (PPO) and QERR# signals are
produced three cycles after the corresponding data inputs.
When used in pairs, the C0 input of the first register is tied
LOW and the C0 input of the second register is tied HIGH. The
Table 1. Parity Function Table
Inputs
RESET#
H
H
H
H
H
H
H
H
H
H
L
DCS#
L
L
L
L
H
H
H
H
H
X
X or
Floating
CSR#
X
X
X
X
L
L
L
L
H
X
X or
Floating
CK
↓↑
↓↑
↓↑
↓↑
↓↑
↓↑
↓↑
↓↑
↓↑
L or H
X or
Floating
CK#
↓↑
↓↑
↓↑
↓↑
↓↑
↓↑
↓↑
↓↑
↓↑
L or H
X or
Floating
Sum of inputs =
H (D1-25)
Even
Odd
Even
Odd
Even
Odd
Even
Odd
X
X
X or Floating
PAR_IN
L
L
H
H
L
L
H
H
X
X
X or
Floating
CY2SSTU32866
C1 input of both registers are tied HIGH. Parity, which arrives
one cycle after the data input to which it applies, is checked on
the PAR_IN input of the first device. The PPO and QERR#
signals are produced on the second device three clock cycles
after the corresponding data inputs. The PPO output of the first
register is cascaded to the PAR_IN of the second register. The
QERR# output of the first register is left floating and the valid
error information is latched on the QERR# output of the
second register. If an error occurs and the QERR# output is
driven LOW, it stays latched LOW for two clock cycles or until
RESET# is driven LOW. The DIMM-dependent signals
(DCKE, DCS#, DODT, and CSR#) are not included in the
parity check computation.
Parity is calculated using
Table 1.
Outputs
PPO
L
H
H
L
L
H
H
L
PPO
0
PPO
0
L
QERR#
H
L
L
H
H
L
L
H
QERR#
0
QERR#
0
H
Pin Definition
Pin Name
GND
Pin Number
(C0 = 0, C1 = 0)
Pin Number
(C0 = 0, C1 = 1)
Pin Number
(C0 = 1, C1 = 1)
Description
B3, B4, D3, D4, F3, F4, B3, B4, D3, D4, F3, B3, B4, D3, D4, F3, Ground
H3, H4, K3, K4, M3, M4, F4, H3, H4, K3, K4, F4, H3, H4, K3, K4,
P3, P4
M3, M4, P3, P4
M3, M4, P3, P4
A4, C3, C4, E3, E4, G3, A4, C3, C4, E3,
G4, J3, J4, L3, L4, N3, E4, G3, G4, J3, J4,
N4, R3, R4, T4
L3, L4, N3, N4, R3,
R4, T4
A3, T3
J5
J6
H1
J1
G6
G5
A3, T3
J5
J6
H1
J1
G6
G5
A4, C3, C4, E3,
Power Supply Voltage
E4, G3, G4, J3, J4,
L3, L4, N3, N4, R3,
R4, T4
A3, T3
J5
J6
H1
J1
G6
G5
Input Reference Voltage
Reserved
Reserved
Positive Master Clock
Negative Master Clock
Configuration control input
Configuration control input
VDD
VREF
ZOH
ZOL
CK
CK#
C0
C1
Document #: 38-07690 Rev. **
Page 2 of 26
PRELIMINARY
Pin Definition
(continued)
Pin Name
RESET#
G2
Pin Number
(C0 = 0, C1 = 0)
Pin Number
(C0 = 0, C1 = 1)
G2
Pin Number
(C0 = 1, C1 = 1)
G2
CY2SSTU32866
Description
Asynchronous reset – resets registers and
disables Vref data and clock differential input
receivers
Chip Select – Disables D1-D24 when both CSR#
and DCS# are HIGH (V
DD
)
Chip Select – Disables D1-D24 when both CSR#
and DCS# are HIGH (V
DD
)
Data input – clocked in on the crossing points of
CK and CK#
Data input – clocked in on the crossing points of
CK and CK#
Data input – clocked in on the crossing points of
CK and CK#
CSR#
DCS#
D1
D2-3
D4
D5, 6, 8, 9,
10
D11
D12, 13
D14
D15-25
DODT
DCKE
Q1A
Q2A-3A
Q4A
J2
H2
J2
H2
J2
H2
A1
B1, C1
B1, C1
B1, C1
D1
E1, F1, K1, L1, M1
N1
P1, R1
T1
B2, C2, E2, F2, K2, L2,
M2, N2, P2, R2, T2
D1
A1
E1, F1, K1, L1, M1 E1, F1, K1, L1, M1 Data input – clocked in on the crossing points of
CK and CK#
N1
P1, R1
T1
P1, R1
Data input – clocked in on the crossing points of
CK and CK#
Data input – clocked in on the crossing points of
CK and CK#
Data input – clocked in on the crossing points of
CK and CK#
Data input – clocked in on the crossing points of
CK and CK#
D1
A1
N1
T1
A5
The outputs of this register bit will not be
suspended by the DCS# and CSR# Control
The outputs of this register bit will not be
suspended by the DCS# and CSR# Control
Data Outputs that are suspended by the DCS#
and CSR# control
Data Outputs that are suspended by the DCS#
and CSR# control
Data Outputs that are suspended by the DCS#
and CSR# control
B5, C5
B5, C5
B5, C5
D5
Q5A, 6A, 8A, E5, F5, K5, L5, M5
9A, 10A
Q11A
Q14A
Q1B
Q2B-3B
Q4B
Q5B, 6B, 8B,
9B, 10B,
Q11B
N5
T5
Q12A, Q13A P5, R5
E5, F5, K5, L5, M5 E5, F5, K5, L5, M5 Data Outputs that are suspended by the DCS#
and CSR# control
N5
P5, R5
T5
A6
B6, C6
B6, C6
D6
P5, R5
Data Outputs that are suspended by the DCS#
and CSR# control
Data Outputs that are suspended by the DCS#
and CSR# control
Data Outputs that are suspended by the DCS#
and CSR# control
Data Outputs that are suspended by the DCS#
and CSR# control
E6, F6, K6, L6, M6 E6, F6, K6, L6, M6 Data Outputs that are suspended by the DCS#
and CSR# control
N6
Data Outputs that are suspended by the DCS#
and CSR# control
Document #: 38-07690 Rev. **
Page 3 of 26
PRELIMINARY
Pin Definition
(continued)
Pin Name
Q12B, 13B
Q14B
Q15-25
QCSA#
QCSB#
QODTA
QODTB
QCKEA
QCKEB
PPO
QERR#
PAR_IN
NC
A2
D2
G1
A6, D6, H6
A5
D5
B6, C6, E6, F6, K6, L6,
M6, N6, P6, R6, T6
H5
H5
H6
D5
D6
A5
A6
A2
D2
G1
H5
H6
N5
N6
T5
T6
A2
D2
G1
Pin Number
(C0 = 0, C1 = 0)
Pin Number
(C0 = 0, C1 = 1)
P6, R6
T6
Pin Number
(C0 = 1, C1 = 1)
P6, R6
CY2SSTU32866
Description
Data Outputs that are suspended by the DCS#
and CSR# control
Data Outputs that are suspended by the DCS#
and CSR# control
Data Outputs that are suspended by the DCS#
and CSR# control
Data outputs that will not be suspended by the
DCS# and CSR# control
Data outputs that will not be suspended by the
DCS# and CSR# control
Data outputs that will not be suspended by the
DCS# and CSR# control
Data outputs that will not be suspended by the
DCS# and CSR# control
Data outputs that will not be suspended by the
DCS# and CSR# control
Data outputs that will not be suspended by the
DCS# and CSR# control
Partial parity out – indicates odd parity of inputs
D1-D25
Output error bit – generated one clock cycle after
the corresponding data output
Parity input – arrives one clock cycle after the
corresponding data input
B2, C2, E2, F2, K2, B2, C2, E2, F2, K2, No Connect Pins
L2, M2, N2, P2,
L2, M2, N2, P2,
R2, T2
R2, T2
Document #: 38-07690 Rev. **
Page 4 of 26
PRELIMINARY
G2
H1
J1
LPS0
(internal node)
D2−D3,
22
D5−D6,
D8-D25
A3, T3
VREF
D2−D3,
D5−D6,
D8−D25
22
22
D2−D3,
D5−D6,
D8−D25
CY2SSTU32866
RESET
CLK
CLK
D
R
CE
CLK
Q
22
Q2−Q3,
Q5−Q6,
Q8−Q25
Parity
Generator
C1
G5
0
D
R
PAR_IN
G1
Q
CLK
R
1
D
Q
CLK
CE
R
D
Q
CLK
1
0
A2
PPO
D2
QERR
C0
G6
CLK
2−Bit
Counter
R
LPS1
(internal node)
0
D
Q
CLK
1
R
Figure 1. Parity logic Diagram for 1:1 register configuration (positive logic) C0=0, C1=0
Document #: 38-07690 Rev. **
Page 5 of 26
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