DS1558
Watchdog Clock with NV RAM Control
www.maxim-ic.com
FEATURES
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Integrated real-time clock (RTC), power-fail
control circuit, and NV RAM controller
Clock registers are accessed identically to the
static RAM; these registers are resident in the
16 top RAM locations
Century register
Greater than 10 years of timekeeping and data
retention in the absence of power with small
lithium coin cell(s) and low-leakage SRAM
Precision power-on reset
Programmable watchdog timer and RTC
alarm
BCD-coded year, month, date, day, hours,
minutes, and seconds with automatic leap-
year compensation valid up to the year 2100
Battery voltage-level indicator flag
Power-fail write protection allows for
±10%
V
CC
power-supply tolerance
Underwriters Laboratory (UL) recognized
PIN CONFIGURATION
TOP VIEW
GND
X1
X2
GND
A17
N.C.
VCC
N.C.
VCCO
NC
RST
VBAT
2
1
2
3
4
5
6
7
8
9
10
11
12
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Package Dimension Information:
www.maxim-ic.com/DallasPackInfo
PIN DESCRIPTION
A0–A18
DQ0–DQ7
IRQ
/FT
RST
CE
CER
OE
OER
WE
ORDERING INFORMATION
PART
DS1558Y
DS1558W
PIN-
PACKAGE
48 TQFP
48 TQFP
V
CC
(V)
5
3.3
TOP
MARK
DS1558B
DS1558D
V
CC
V
CCO
GND
N.C.
X1, X2
V
BAT1
V
BAT2
Note:
Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here:
www.maxim-ic.com/errata..
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N.C.
A0
DQ0
DQ1
DQ2
GND
DQ3
DQ4
DQ5
DQ6
DQ7
CER
13
14
15
16
17
18
19
20
21
22
23
24
N.C.
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
DS1558
A15
VBAT1
WE
IRQ/FT
A13
A8
A9
A11
OE
A10
CE
OER
TQFP
- Address Input
- Data Input/Outputs
- Interrupt, Frequency-Test
Output (Open Drain)
- Power-On Reset Output
(Open Drain)
- Chip-Enable Input
- Chip-Enable RAM
- Output-Enable Input
- Output-Enable RAM
- Write Enable
- Power-Supply Input
- V
CC
Out to RAM
- Ground
- No Connection
- Crystal Connection
- +3V Battery Input
- +3V Battery Input
REV: 082503
DS1558
TYPICAL OPERATING CIRCUIT
DESCRIPTION
The DS1558 is a full function, year 2000-compliant (Y2KC), real-time clock/calendar with an RTC
alarm, watchdog timer, power-on reset, battery monitor, and NV SRAM controller. User access to all
registers within the DS1558 is accomplished with a byte-wide interface as shown in Figure 1. The RTC
registers contain century, year, month, date, day, hours, minutes, and seconds data in 24-hour BCD
format. Corrections for day of month and leap year are made automatically.
The DS1558 maps the RTC registers into the SRAM address space and constantly monitors A0–A18.
When any of the upper 16 address locations are accessed, the DS1558 inhibits
CER
and
OER
to the
SRAM, and redirects reads and writes to the RTC registers within the DS1558. The DS1558 can be used
with SRAMs up to 524,272 addresses. Smaller SRAMs can be used, provided that the unused upper
address lines on the DS1558 are connected to V
CC
.
The RTC registers are double-buffered into an internal and external set. The user has direct access to the
external set. Clock/calendar updates to the external set of registers can be disabled and enabled to allow
the user to access static data. Assuming the internal oscillator is turned on, the internal set of registers is
continuously updated; this occurs regardless of external register settings to guarantee that accurate RTC
information is always maintained.
The DS1558 has interrupt (
IRQ
/FT) and reset (
RST
) outputs that can be used to control CPU activity.
The
IRQ
/FT interrupt output can be used to generate an external interrupt when the RTC register values
match user-programmed alarm values. The interrupt is always available while the device is powered from
the system supply, and it can be programmed to occur when in the battery-backed state to serve as a
system wake-up. The
IRQ
/FT output can also be used as a CPU watchdog timer. CPU activity is
monitored and an interrupt or reset output are activated if the correct activity is not detected within
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DS1558
programmed limits. The DS1558 power-on reset can be used to detect a system power-down or failure
and hold the CPU in a safe reset state until normal power returns and stabilizes; the
RST
output is used
for this function.
The DS1558 also contains its own power-fail circuitry, which automatically protects the data in the clock
and SRAM against out-of-tolerance V
CCI
conditions by inhibiting the
CE
input when the V
CC
supply
enters an out-of-tolerance condition. When V
CCI
goes below the level of V
BAT
, the external battery is
switched on to supply energy to the clock and the external SRAM. This feature provides a high degree of
data security during unpredictable system operation brought on by low V
CC
levels.
Figure 1. BLOCK DIAGRAM
Note:
Any unused upper address pins must be connected to V
CC
to properly address the RTC.
SIGNAL DESCRIPTIONS
A0–A18
– Address inputs for address decode. The DS1558 uses the address inputs to determine whether
or not a read or write cycle should be directed to the attached SRAM or to the RTC registers.
DQ0–DQ7
– Data input/output pins for the RTC registers.
IRQ
/FT
– This pin is used to output the alarm interrupt or the frequency test signal. It is open drain and
requires an external pullup resistor.
RST
– This pin is an output used to signal that V
CC
is out of tolerance. On power-up,
RST
is held low for
a period of time to allow the system to stabilize. The RTC and SRAM are not accessible while
RST
is
active. This pin is open drain and requires an external pullup resistor.
CE
– Chip-enable input that is used to access the RTC and the external SRAM.
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DS1558
– Chip-enable RAM output.
CE
is passed through to
CER
, with an added propagation delay. When
the signals on A0–A18 match an RTC address,
CER
is held high, disabling the SRAM. If
OE
is also low,
the RTC outputs data on DQ0–DQ7.
CER
OE
– Output-enable input that is used to access the RTC and the external SRAM.
– Output-enable RAM output.
OE
is passed through to
OER
, with an added propagation delay.
When the signals on A0–A18 match an RTC address,
CER
is held high, disabling the SRAM. If
CE
is
also low, the RTC outputs data on DQ0–DQ7.
OER
WE
– Write-enable input that is used to write data to the RTC registers.
V
CC
, GND
– DC power is provided to the device on these pins. V
CC
is the +5V input. When 5V (or 3.3V
for the 3.3V version) is applied within normal limits, the device is fully accessible and data can be written
and read. Reads and writes are inhibited when a 3V battery is connected to the device and V
CC
is V
TP
.
However, the timekeeping function continues unaffected by the lower input voltage. As V
CC
falls below
V
BAT
, the RAM and RTC are switched over to the external power supply (nominal 3.0V DC) at V
BAT
.
V
CCO
– V
CC
output to RAM. While V
CC
is above V
BAT
, the external SRAM is powered by V
CC
. When
V
CC
is below the battery level, the SRAM is powered by one of the V
BAT
inputs.
N.C.
– No internal connection.
X1, X2
– Connections for a standard 32.768kHz quartz crystal. The internal oscillator circuitry is
designed for operation with a crystal having a specified load capacitance (C
L
) of 6pF. For more
information about crystal selection and crystal layout considerations, refer to
Application Note 58
“Crystal Considerations with Dallas Real-Time Clocks.” The DS1558 can also be driven by an external
32.768kHz oscillator. In this configuration, the X1 pin is connected to the external oscillator signal and
the X2 pin is floated.
V
BAT1
, V
BAT2
– Battery inputs for any standard 3V lithium cell or other energy source. Battery voltage
must be held between 2.5V and 3.7V for proper operation. UL recognized to ensure against reverse
charging current when used with a lithium battery. If only one battery is used, it should be attached to
V
BAT1
, and V
BAT2
should be grounded.
See “Conditions of Acceptability” at
http://www.maxim-ic.com/TechSupport/QA/ntrl.htm.
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DS1558
Table 1. OPERATING MODES
V
CC
V
CC
> V
PF
V
SO
< V
CC
< V
PF
V
CC
< V
SO
< V
PF
CE
OE
WE
V
IH
V
IL
V
IL
V
IL
X
X
X
X
V
IL
V
IH
X
X
X
V
IL
V
IH
V
IH
X
X
DQ0–DQ7
High-Z
D
IN
D
OUT
High-Z
High-Z
High-Z
MODE
Deselect
Write
Read
Read
Deselect
Data Retention
POWER
Standby
Active
Active
Active
CMOS Standby
Battery Current
DATA READ MODE
The DS1558 is in the read mode whenever
CE
is low and
WE
is high. The device architecture allows
ripple-through access to any valid address location. Valid data is available at the DQ pins within t
AA
after
the last address input is stable, provided that
CE
and
OE
access times are satisfied. If
CE
or
OE
access
times are not met, valid data is available at the latter of chip-enable access (t
CEA
) or at output-enable
access time (t
OEA
). The state of the data input/output pins (DQ) is controlled by
CE
and
OE
. If the
outputs are activated before t
AA
, the data lines are driven to an intermediate state until t
AA
. If the address
inputs are changed while
CE
and
OE
remain valid, output data remains valid for output-data hold time
(t
OH
), but then goes indeterminate until the next address access.
DATA WRITE MODE
The DS1558 is in the write mode whenever
WE
and
CE
are in their active state. The start of a write is
referenced to the latter occurring transition of
WE
or
CE
. The addresses must be held valid throughout
the cycle.
CE
and
WE
must return inactive for a minimum of t
WR
prior to the initiation of a subsequent
read or write cycle. Data in must be valid t
DS
prior to the end of the write and remain valid for t
DH
afterward. In a typical application, the
OE
signal is high during a write cycle. However,
OE
can be active
provided that care is taken with the data bus to avoid bus contention. If
OE
is low prior to
WE
transitioning low, the data bus can become active with read data defined by the address inputs. A low
transition on
WE
then disables the outputs t
WEZ
after
WE
goes active.
DATA RETENTION MODE
The 5V device is fully accessible and data can be written and read only when V
CC
is greater than V
PF
.
However, when V
CC
is below the power-fail point V
PF
(point at which write protection occurs), the
internal clock registers and SRAM are blocked from any access. When V
CC
falls below the battery switch
point V
SO
(battery supply level), device power is switched from the V
CC
pin to the backup battery. RTC
operation and SRAM data are maintained from the battery until V
CC
is returned to nominal levels.
The 3.3V device is fully accessible and data can be written and read only when V
CC
is greater than V
PF
.
When V
CC
falls below V
PF
, access to the device is inhibited. If V
PF
is less than V
SO
, the device power is
switched from V
CC
to the internal backup lithium battery when V
CC
drops below V
PF
. If V
PF
is greater
than V
SO
, the device power is switched from V
CC
to the internal backup lithium battery when V
CC
drops
below V
SO
. RTC operation and SRAM data are maintained from the battery until V
CC
is returned to
nominal levels.
All control, data, and address signals must be powered down when V
CC
is powered down.
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