XX-XXXX; Rev 1; 11/03
3V 10-Tap Silicon Delay Line
General Description
The DS1110L 10-tap delay line is a 3V version of the
DS1110. It has 10 equally spaced taps providing delays
from 10ns to 500ns. The DS1110L series delay lines
provide a nominal accuracy of ±5% or ±2ns, whichever
is greater, at 3.3V and +25°C. The DS1110L is character-
ized to operate from 2.7V to 3.6V. The DS1110L
produces both leading- and trailing-edge delays with
equal precision. The device is offered in a standard
14-pin TSSOP.
♦
All-Silicon Delay Line
♦
3V Version of the DS1110
♦
10 Taps Equally Spaced
♦
Delays Are Stable and Precise
♦
Leading- and Trailing-Edge Accuracy
♦
Delay Tolerance ±5% or ±2ns, Whichever Is
Greater, at 3.3V and +25°C
♦
Economical
♦
Low-Profile 14-Pin TSSOP
♦
Low-Power CMOS
♦
TTL/CMOS Compatible
♦
Vapor Phase and IR Solderable
♦
Fast-Turn Prototypes
♦
Delays Specified Over Commercial and Industrial
Temperature Ranges
♦
Custom Delays Available
Features
DS1110L
Applications
Communications Equipment
Medical Devices
Automated Test Equipment
PC Peripheral Devices
Pin Configuration
PART
Ordering Information
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
PIN-
PACKAGE
14 TSSOP (173mil)
14 TSSOP (173mil)
14 TSSOP (173mil)
14 TSSOP (173mil)
14 TSSOP (173mil)
14 TSSOP (173mil)
14 TSSOP (173mil)
14 TSSOP (173mil)
14 TSSOP (173mil)
14 TSSOP (173mil)
14 TSSOP (173mil)
TOTAL
DELAY
(ns) *
100
125
150
175
200
250
300
350
400
450
500
TOP VIEW
IN 1
N.C.
TAP2
2
3
14 V
CC
13 TAP1
DS1110LE-100
DS1110LE-125
DS1110LE-150
DS1110LE-175
DS1110LE-200
DS1110LE-250
DS1110LE-300
DS1110LE-350
DS1110LE-400
DS1110LE-450
DS1110LE-500
DS1110L
12 TAP3
11 TAP5
10 TAP7
9
8
TAP9
TAP10
TAP4 4
TAP6 5
TAP8 6
GND 7
TSSOP (173mil)
*Custom delays are available.
_____________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
3V 10-Tap Silicon Delay Line
DS1110L
ABSOLUTE MAXIMUM RATINGS
Voltage on Any Pin Relative to Ground .................-0.5V to +6.0V
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-55°C to +125°C
Soldering Temperature...................See IPC/JEDEC J-STD-020A
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(-40°C to +85°C, V
CC
= 2.7V to 3.6V.)
PARAMETER
Supply Voltage
High-Level Input Voltage
Low-Level Input Voltage
Input Leakage Current
Active Current
High-Level Output Current
Low-Level Output Current
SYMBOL
V
CC
V
IH
V
IL
I
I
I
CC
I
OH
I
OL
(Note 1)
(Note 1)
(Note 1)
0V
≤
V
I
≤
V
CC
V
CC
= max, period = min (Note 2)
V
CC
= min, V
OH
= 2.3V
V
CC
= min, V
OL
= 0.5V
12
CONDITIONS
MIN
2.7
2.2
-0.3
-1.0
40
TYP
3.3
MAX
3.6
V
CC
+ 0.3
+0.8
+1.0
150
-1.0
UNITS
V
V
V
µA
mA
mA
mA
AC ELECTRICAL CHARACTERISTICS
(-40°C to +85°C, V
CC
= 2.7V to 3.6V.)
PARAMETER
Input Pulse Width
Input to Tap Delay
(Delays
≤
40ns)
Input to Tap Delay
(Delays > 40ns)
Power-Up Time
Input Period
SYMBOL
t
WI
t
PLH
t
PHL
t
PLH
t
PHL
t
PU
Period
(Note 8)
2 (t
WI
)
(Note 6)
+25°C, 3.3V (Notes 3, 5, 6, 7, 9)
0°C to +70°C (Notes 4–7)
-40°C to +85°C (Notes 4–7)
+25°C, 3.3V (Notes 3, 5, 6, 7, 9)
0°C to +70°C (Notes 4–7)
-40°C to +85°C (Notes 4–7)
CONDITIONS
MIN
10% of
tap 10
-2
-3
-4
-5
-8
-13
Table 1
Table 1
Table 1
Table 1
Table 1
Table 1
+2
+3
+4
+5
+8
+13
100
ms
ns
%
ns
TYP
MAX
UNITS
ns
2
______________________________________________________________________
3V 10-Tap Silicon Delay Line
CAPACITANCE
(T
A
= +25°C.)
PARAMETER
Input Capacitance
SYMBOL
C
IN
CONDITIONS
MIN
TYP
5
MAX
10
UNITS
pF
DS1110L
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
All voltages are referenced to ground.
Measured with outputs open.
Initial tolerances are ± with respect to the nominal value at +25°C and V
CC
= 3.3V for both leading and trailing edges.
Temperature and voltage tolerances are with respect to the nominal delay value over stated temperature range and a 2.7V to
3.6V range.
Intermediate delay values are available on a custom basis.
See
Test Conditions
section.
All tap delays tend to vary unidirectionally with temperature or voltage changes. For example, if tap 1 slows down, all other
taps also slow down; tap 3 can never be faster than tap 2.
Pulse width and period specifications may be exceeded; however, accuracy is application sensitive (decoupling, layout, etc.).
For Tap 1 delays greater than 20ns, the tolerance is ±3ns or ±5%, whichever is greater.
Typical Operating Characteristics
(V
CC
= 3.3V, T
A
= +25°C, unless otherwise noted.)
DELAY CHANGE (%)
vs. V
CC
DS1110L-500
DS1110L toc01
DELAY CHANGE (%)
vs. V
CC
DS1110L-250
0.2
CHANGE IN DELAY (%)
0.1
0
-0.1
-0.2
-0.3
-0.4
RAISING EDGE
FALLING EDGE
DS1110L toc02
0.10
0.05
CHANGE IN DELAY (%)
0
-0.05
-0.10
-0.15
-0.20
-0.25
-0.30
-0.35
2.7
3.0
V
CC
(V)
3.3
RAISING EDGE
FALLING EDGE
0.3
3.6
2.7
3.0
V
CC
(V)
3.3
3.6
CHANGE IN DELAY (%) vs. TEMPERATURE
DS1110L-500
DS1110L toc03
CHANGE IN DELAY (%) vs. TEMPERATURE
DS1110L-250
DS1110L toc04
6
5
4
CHANGE IN DELAY (%)
3
2
1
0
-1
-2
-3
-4
-5
-40
-15
10
35
60
RISING EDGE
FALLING EDGE
4
3
CHANGE IN DELAY (%)
2
1
0
-1
-2
-3
RISING EDGE
FALLING EDGE
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
_____________________________________________________________________
3
3V 10-Tap Silicon Delay Line
DS1110L
Typical Operating Characteristics (continued)
(V
CC
= 3.3V, T
A
= +25°C, unless otherwise noted.)
OUTPUT CURRENT HIGH
vs. OUTPUT VOLTAGE HIGH
DS1110L toc05
OUTPUT CURRENT LOW
vs. OUTPUT VOLTAGE LOW
1.60E-02
OUTPUT CURRENT LOW (A)
1.40E-02
1.20E-02
1.00E-02
8.00E-03
6.00E-03
4.00E-03
2.00E-03
0.00E+00
V
CC
= 2.7V
DS1110L toc06
0.00E+0
-2.00E-03
OUTPUT CURRENT HIGH (A)
-4.00E-03
-6.00E-03
-8.00E-03
-1.00E-02
-1.20E-02
-1.40E-02
-1.60E-02
-1.80E-02
2.0
2.1
2.2
2.3
2.4
2.5
2.6
V
CC
= 2.7V
1.80E-02
2.7
0
0.1
0.2
0.3
0.4
0.5
0.6
OUTPUT VOLTAGE HIGH (V)
OUTPUT VOLTAGE LOW (V)
ACTIVE CURRENT vs. INPUT FREQUENCY
DS1110L-250
45
40
35
CURRENT (mA)
30
25
20
15
10
5
0
0.1
1
10
100
FREQUENCY (MHz)
V
CC
= 3.6V
15pF LOAD
ON EACH TAP
5
DS1110L toc07
ACTIVE CURRENT vs. INPUT FREQUENCY
DS1110L-500
DS1110L toc08
50
25
20
CURRENT (mA)
15
10
V
CC
= 3.6V
15pF LOAD
ON EACH TAP
0.1
1.0
FREQUENCY (MHz)
10
0
Pin Description
PIN
1
2
7
13, 3, 12, 4, 11,
5, 10, 6, 9, 8
14
NAME
IN
N.C.
GND
Tap 1–Tap 10
VCC
Input
No Connection
Ground
Tap Output Number
2.7V to 3.6V
FUNCTION
4
______________________________________________________________________
3V 10-Tap Silicon Delay Line
Detailed Description
The DS1110L 10-tap delay line is a 3V version of
the DS1110. It has 10 equally spaced taps providing
delays from 10ns to 500ns. The device is offered in a
standard 14-pin TSSOP. The DS1110L series delay lines
provide a nominal accuracy of ±5% or ±2ns, whichever is
greater, at 3.3V and +25°C. The DS1110L is character-
ized to operate from 2.7V to 3.6V. The DS1110L repro-
duces the input-logic state at the tap 10 output after a
fixed delay as specified by the dash-number suffix of the
part number (Table
1).
The DS1110L produces both lead-
ing- and trailing-edge delays with equal precision. Each
tap is capable of driving up to 10 74LS-type loads. Dallas
Semiconductor can customize standard products to meet
specific needs. Figure 1 is the DS1110_L logic diagram
and Figure 2 shows the timing diagram for the silicon
delay line.
DS1110L
Table 1. Part Number by Delay (t
PHL
, t
PLH
)
PART
DS1110LE-100
DS1110LE-125
DS1110LE-150
DS1110LE-175
DS1110LE-200
DS1110LE-250
DS1110LE-300
DS1110LE-350
DS1110LE-400
DS1110LE-450
DS1110LE-500
TOTAL DELAY (ns)
100
125
150
175
200
250
300
350
400
450
500
DELAY/TAP (ns)
10
12.5
15
17.5
20
25
30
35
40
45
50
TAP1
TAP2
TAP9
TAP10
IN
10%
10%
10%
10%
Figure 1. Logic Diagram
PERIOD
t
RISE
t
FALL
V
IH
2.4V
1.5V
0.6V
2.4V
1.5V
0.6V
1.5V
IN V
IL
t
WI
t
WI
t
PLH
t
PLH
1.5V
OUT
1.5V
Figure 2. Timing Diagram: Silicon Delay Line
_____________________________________________________________________
5
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