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CY7C1418JV18
CY7C1420JV18
36-Mbit DDR II SRAM 2-Word
Burst Architecture
Features
■
■
■
■
■
Functional Description
The CY7C1418JV18 and CY7C1420JV18 are 1.8V
Synchronous Pipelined SRAM equipped with DDR II archi-
tecture. The DDR II consists of an SRAM core with advanced
synchronous peripheral circuitry and a 1-bit burst counter.
Addresses for read and write are latched on alternate rising
edges of the input (K) clock. Write data is registered on the rising
edges of both K and K. Read data is driven on the rising edges
of C and C if provided, or on the rising edge of K and K if C/C are
not provided. On CY7C1418JV18 and CY7C1420JV18, the
burst counter takes in the least significant bit of the external
address and bursts two 18-bit words in the case of
CY7C1418JV18 and two 36-bit words in the case of
CY7C1420JV18 sequentially into or out of the device.
Asynchronous inputs include an output impedance matching
input (ZQ). Synchronous data outputs (Q, sharing the same
physical pins as the data inputs D) are tightly matched to the two
output echo clocks CQ/CQ, eliminating the need for separately
capturing data from each individual DDR SRAM in the system
design. Output data clocks (C/C) enable maximum system
clocking and data synchronization flexibility.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
36-Mbit density (2M x 18, 1M x 36)
300 MHz clock for high bandwidth
2-word burst for reducing address bus frequency
Double Data Rate (DDR) interfaces
(data transferred at 600 MHz) at 300 MHz for DDR II
Two input clocks (K and K) for precise DDR timing
❐
SRAM uses rising edges only
Two input clocks for output data (C and C) to minimize clock
skew and flight time mismatches
Echo clocks (CQ and CQ) simplify data capture in high speed
systems
Synchronous internally self-timed writes
DDR II operates with 1.5 cycle read latency when DLL is
enabled
Operates similar to a DDR I device with 1 cycle read latency in
DLL off mode
1.8V core power supply with HSTL inputs and outputs
Variable drive HSTL output buffers
Expanded HSTL output voltage (1.4V–V
DD
)
Available in 165-ball FBGA package (15 x 17 x 1.4 mm)
Offered in both in Pb-free and non Pb-free packages
JTAG 1149.1 compatible test access port
Delay Lock Loop (DLL) for accurate data placement
■
■
■
■
■
■
■
■
■
■
■
■
Configurations
CY7C1418JV18 – 2M x 18
CY7C1420JV18 – 1M x 36
Selection Guide
Description
Maximum Operating Frequency
Maximum Operating Current
x18
x36
300 MHz
300
975
1010
250 MHz
250
760
825
Unit
MHz
mA
Cypress Semiconductor Corporation
Document Number: 001-12558 Rev. *H
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised October 20, 2010
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CY7C1418JV18
CY7C1420JV18
Logic Block Diagram (CY7C1418JV18)
A0
Burst
Logic
A
(20:0)
21
LD
K
K
20
Write Add. Decode
Read Add. Decode
A
(20:1)
Address
Register
Write
Reg
1M x 18 Array
Write
Reg
18
1M x 18 Array
CLK
Gen.
Output
Logic
Control
R/W
C
C
CQ
DOFF
Read Data Reg.
36
18
Control
Logic
18
Reg.
Reg.
Reg. 18
V
REF
R/W
BWS
[1:0]
CQ
18
DQ
[17:0]
18
Logic Block Diagram (CY7C1420JV18)
A0
Burst
Logic
A
(19:0)
20
LD
K
K
19
Write Add. Decode
Read Add. Decode
A
(19:1)
Address
Register
Write
Reg
512K x 36 Array
Write
Reg
512K x 36 Array
36
CLK
Gen.
Output
Logic
Control
R/W
C
C
CQ
DOFF
Read Data Reg.
72
36
Control
Logic
36
Reg.
Reg.
Reg. 36
V
REF
R/W
BWS
[3:0]
CQ
36
DQ
[35:0]
36
Document Number: 001-12558 Rev. *H
Page 2 of 26
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CY7C1418JV18
CY7C1420JV18
Contents
Features ............................................................................ 1
Configurations .................................................................. 1
Functional Description ..................................................... 1
Selection Guide ................................................................ 1
Logic Block Diagram (CY7C1418JV18) .......................... 2
Logic Block Diagram (CY7C1420JV18) .......................... 2
Pin Configuration ............................................................. 4
165-Ball FBGA (15 x 17 x 1.4 mm) Pinout .................. 4
Pin Definitions .................................................................. 5
Functional Overview ........................................................ 7
Read Operations for DDR II ........................................ 7
Write Operations ......................................................... 7
Byte Write Operations ................................................. 7
Single Clock Mode ...................................................... 7
DDR Operation ............................................................ 7
Depth Expansion ......................................................... 8
Programmable Impedance .......................................... 8
Echo Clocks ................................................................ 8
DLL .............................................................................. 8
Application Example ........................................................ 8
Truth Table ........................................................................ 9
Burst Address Table
(CY7C1418JV18, CY7C1420JV18) .................................... 9
Write Cycle Descriptions ................................................. 9
Write Cycle Descriptions ............................................... 10
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 11
Disabling the JTAG Feature ...................................... 11
Test Access Port—Test Clock ................................... 11
Test Mode Select (TMS) ........................................... 11
Test Data-In (TDI) ..................................................... 11
Test Data-Out (TDO) ................................................. 11
Performing a TAP Reset ........................................... 11
TAP Registers ........................................................... 11
TAP Instruction Set ................................................... 11
TAP Controller State Diagram ....................................... 13
TAP Controller Block Diagram ...................................... 14
TAP Electrical Characteristics ...................................... 14
TAP AC Switching Characteristics ............................... 15
TAP Timing and Test Conditions .................................. 15
Identification Register Definitions ................................ 16
Scan Register Sizes ....................................................... 16
Instruction Codes ........................................................... 16
Boundary Scan Order .................................................... 17
Power Up Sequence in DDR II SRAM ........................... 18
Power Up Sequence ................................................. 18
DLL Constraints ........................................................ 18
Maximum Ratings ........................................................... 19
Operating Range ............................................................ 19
Electrical Characteristics .............................................. 19
DC Electrical Characteristics ..................................... 19
AC Electrical Characteristics ..................................... 20
Capacitance .................................................................... 20
Thermal Resistance ....................................................... 20
Switching Characteristics ............................................. 21
Switching Waveforms .................................................... 22
Ordering Information ..................................................... 23
Ordering Code Definitions ....................................... 23
Package Diagram ........................................................... 24
Document History Page ................................................. 25
Sales, Solutions, and Legal Information ...................... 26
Worldwide Sales and Design Support ....................... 26
Products .................................................................... 26
PSoC Solutions ......................................................... 26
Document Number: 001-12558 Rev. *H
Page 3 of 26
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CY7C1418JV18
CY7C1420JV18
Pin Configuration
The pin configuration for CY7C1418JV18, and CY7C1420JV18 follow.
[1]
165-Ball FBGA (15 x 17 x 1.4 mm) Pinout
CY7C1418JV18 (2M x 18)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
NC/72M
DQ9
NC
NC
NC
DQ12
NC
V
REF
NC
NC
DQ15
NC
NC
NC
TCK
3
A
NC
NC
DQ10
DQ11
NC
DQ13
V
DDQ
NC
DQ14
NC
NC
DQ16
DQ17
A
4
R/W
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
5
BWS
1
NC/288M
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
K
K
A0
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C
7
NC/144M
BWS
0
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
LD
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
9
A
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
A
10
A
NC
DQ7
NC
NC
NC
NC
V
REF
DQ4
D3
NC
DQ1
NC
NC
TMS
11
CQ
DQ8
NC
NC
DQ6
DQ5
NC
ZQ
NC
DQ3
DQ2
NC
NC
DQ0
TDI
CY7C1420JV18 (1M x 36)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
NC/144M
DQ27
NC
DQ29
NC
DQ30
DQ31
V
REF
NC
NC
DQ33
NC
DQ35
NC
TCK
3
A
DQ18
DQ28
DQ19
DQ20
DQ21
DQ22
V
DDQ
DQ32
DQ23
DQ24
DQ34
DQ25
DQ26
A
4
R/W
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
5
BWS
2
BWS
3
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
K
K
A0
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C
7
BWS
1
BWS
0
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
LD
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
9
A
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
A
10
NC/72M
NC
DQ17
NC
DQ15
NC
NC
V
REF
DQ13
DQ12
NC
DQ11
NC
DQ9
TMS
11
CQ
DQ8
DQ7
DQ16
DQ6
DQ5
DQ14
ZQ
DQ4
DQ3
DQ2
DQ1
DQ10
DQ0
TDI
Note
1. NC/72M, NC/144M, and NC/288M are not connected to the die and can be tied to any voltage level.
Document Number: 001-12558 Rev. *H
Page 4 of 26
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