• Zero input-output propagation delay, adjustable by
loading on CLKOUT pin
• Multiple low-skew outputs
— 45 ps typical output-output skew
— 70 ps typical part-to-part skew
— One input drives five outputs (CY23EP05)
— One input drives nine outputs, grouped as 4 + 4 + 1
(CY23EP09)
• 25 ps typical cycle-to-cycle jitter
• 15 ps typical period jitter
• Standard and High drive strength options
• Available in space-saving 16-pin 150-mil SOIC or
4.4-mm TSSOP packages (CY23EP09), and 8-pin,
150-mil SOIC package (CY23EP05) or 8-pin, 4.4mm
TSSOP package (CY23EP05-1)
• 3.3V or 2.5V operation
• Industrial temperature available
of the CY23EP09. It accepts one reference input, and drives
out five low-skew clocks. The -1H versions of each device
operate at up to 220 (200) MHz frequencies at 3.3V (2.5V),
and have higher drive than the -1 devices. All parts have
on-chip PLLs which lock to an input clock on the REF pin. The
PLL feedback is on-chip and is obtained from the CLKOUT
pad.
The CY23EP09 has two banks of four outputs each, which can
be controlled by the Select inputs as shown in the “Select Input
Decoding” table on page 2. If all output clocks are not required,
BankB can be three-stated. The select inputs also allow the
input clock to be directly applied to the outputs for chip and
system testing purposes (CY23EP09).
The CY23EP05 and CY23EP09 PLLs enter a power-down
mode when there are no rising edges on the REF input. In this
state, the outputs are three-stated and the PLL is turned off,
resulting in less than 25
µA
of current draw.
In the special case when S2:S1 is 1:0, the PLL is bypassed
and REF is output from DC to the maximum allowable
frequency. The part behaves like a non-zero delay buffer in this
mode, and the outputs are not tri-stated.
The CY23EP05/CY23EP09 is available in different configura-
tions, as shown in the Ordering Information table. The
CY23EP05-1/CY23EP09-1 is the base part. The
CY23EP05-1H/ CY23EP09-1H is the high-drive version of the
-1, and its rise and fall times are much faster than the -1.
These parts are not intended for 5V input-tolerant applications
Functional Description
The CY23EP09 is a 2.5V or 3.3V zero delay buffer designed
to distribute high-speed clocks and is available in a 16-pin
SOIC or TSSOP package. The CY23EP05 is an 8-pin version
Block Diagram
PLL
REF
CLKOUT
CLKA1
CLKA2
CLKA3
CLKA4
S2
Select Input
Decoding
(CY23EP09 only)
CLKB1
CLKB2
CLKB3
CLKB4
Pin Configuration
MUX
CY23EP09
Top View
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
REF
CLKA1
CLKA2
V
DD
GND
CLKB1
CLKB2
S2
CLKOUT
CLKA4
CLKA3
V
DD
GND
CLKB4
CLKB3
S1
CY23EP05
Top View
REF
CLK2
CLK1
GND
1
2
3
4
8
7
6
5
S1
CLKOUT
CLK4
V
DD
CLK3
Cypress Semiconductor Corporation
Document #: 38-07706 Rev. *B
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Revised March 14, 2005
PRELIMINARY
Pin Definition for CY23EP09
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
REF
[1]
CLKA1
V
DD
GND
CLKB1
[2]
CLKB2
[2]
S2
[3]
S1
[3]
CLKB3
GND
V
DD
CLKA3
[2]
CLKA4
[2]
CLKOUT
[2]
[2]
[2]
CY23EP05
CY23EP09
Description
Signal
Input reference frequency
Buffered clock output, Bank A
Buffered clock output, Bank A
3.3V or 2.5V supply
Ground
Buffered clock output, Bank B
Buffered clock output, Bank B
Select input, bit 2
Select input, bit 1
Buffered clock output, Bank B
Buffered clock output, Bank B
Ground
3.3V or 2.5V supply
Buffered clock output, Bank A
Buffered clock output, Bank A
CLKA2
[2]
CLKB4
[2]
Buffered output, internal feedback on this pin
Pin Description for CY23EP05
Pin
1
2
3
4
5
6
7
8
REF
[1]
CLK2
[2]
CLK1
[2]
GND
CLK3
[2]
V
DD
CLK4
[2]
CLKOUT
[2]
Signal
Input reference frequency
Buffered clock output
Buffered clock output
Ground
Buffered clock output
3.3V or 2.5Vsupply
Buffered clock output
Buffered clock output, internal feedback on this pin
Description
Select Input Decoding for CY23EP09
S2
0
0
1
1
S1
0
1
0
1
CLOCK A1–A4
Three-state
Driven
Driven
Driven
CLOCK B1–B4
Three-state
Three-state
Driven
Driven
CLKOUT
[4]
Driven
Driven
Driven
Driven
Output Source
PLL
PLL
Reference
PLL
PLL Shutdown
N
N
Y
N
Zero Delay and Skew Control
All outputs should be uniformly loaded to achieve Zero Delay
between the input and output. Since the CLKOUT pin is the
internal feedback to the PLL, its relative loading can adjust the
input-output delay.
The output driving the CLKOUT pin will be driving a total load
of 5 pF plus any additional load externally connected to this
pin. For applications requiring zero input-output delay, the total
load on each output pin (including CLKOUT) must be the
same. If input-output delay adjustments are required, the
CLKOUT load may be changed to vary the delay between the
REF input and remaining outputs.
For zero output-output skew, be sure to load all outputs
equally. For further information refer to the application note
entitled “CY2305 and CY2309 as PCI and SDRAM Buffers”.
Notes:
1. Weak pull-down.
2. Weak pull-down on all outputs.
3. Weak pull-ups on these inputs (CY23EP09 only).
4. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and output.
Document #: 38-07706 Rev. *B
Page 2 of 13
PRELIMINARY
Absolute Maximum Conditions
Supply Voltage to Ground Potential ............... –0.5V to +4.6V
DC Input Voltage...................................... V
SS
– 0.5V to 4.6V
CY23EP05
CY23EP09
Storage Temperature .................................. –65°C to +150°C
Junction Temperature .................................................. 150°C
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