D ts e t
aa h e
R c e t r lc r nc
o h se Ee to is
Ma u a t r dCo o e t
n fc u e
mp n n s
R c e tr b a d d c mp n ns ae
o h se rn e
o oet r
ma ua trd u ig ete dewaes
n fcue sn i r i/ fr
h
p rh s d f m te oiia s p l r
uc a e r
o h r n l u pi s
g
e
o R c e tr waes rce td f m
r o h se
fr e rae r
o
te oiia I. Al rce t n ae
h
r nl P
g
l e rai s r
o
d n wi tea p o a o teOC
o e t h p rv l f h
h
M.
P r aetse u igoiia fcoy
at r e td sn r n la tr
s
g
ts p o rmso R c e tr e eo e
e t rga
r o h se d v lp d
ts s lt n t g aa te p o u t
e t oui s o u rne
o
rd c
me t o e c e teOC d t s e t
es r x e d h
M aa h e.
Qu l yOv riw
ai
t
e ve
• IO- 0 1
S 90
•A 92 cr ct n
S 1 0 et ai
i
o
• Qu l e Ma ua trr Ls (
ai d
n fcues it QML MI- R -
) LP F
385
53
•C a sQ Mitr
ls
lay
i
•C a sVS a eL v l
ls
p c ee
• Qu l e S p l r Ls o D sr uos( L )
ai d u pi s it f it b tr QS D
e
i
•R c e trsacic l u pir oD A a d
o h se i
r ia s p l t L n
t
e
me t aln u t a dD A sa d r s
es lid sr n L tn ad .
y
R c e tr lcrnc , L i c mmi e t
o h se Ee t is L C s o
o
tdo
t
s p ligp o u t ta s t f c so r x e t-
u pyn rd cs h t ai y u tme e p ca
s
t n fr u lya daee u loto eoiial
i s o q ai n r q a t h s r n l
o
t
g
y
s p l db id sr ma ua trr.
u pi
e yn ut
y n fcues
T eoiia ma ua trr d ts e t c o a yn ti d c me t e e t tep r r n e
h r n l n fcue’ aa h e a c mp n ig hs o u n r cs h ef ma c
g
s
o
a ds e ic t n o teR c e tr n fcue v rino ti d vc . o h se Ee t n
n p c ai s f h o h se ma ua trd eso f hs e ie R c e tr lcr -
o
o
isg aa te tep r r n eo i s mio d co p o u t t teoiia OE s e ic -
c u rne s h ef ma c ft e c n u tr rd cs o h r n l M p c a
o
s
g
t n .T pc lv le aefr eee c p r o e o l. eti mii m o ma i m rt g
i s ‘y ia’ au s r o rfrn e up s s ny C r n nmu
o
a
r xmu ai s
n
ma b b s do p o u t h rceiain d sg , i lt n o s mpetsig
y e a e n rd c c aa tr t , e in smuai , r a l e t .
z o
o
n
© 2 1 R cetr l t n s LC Al i t R sre 0 1 2 1
0 3 ohs E cr i , L . lRg s eevd 7 1 0 3
e e oc
h
T l r m r, l s v iw wrcl . m
o e n oe p ae it w . e c o
a
e
s
o ec
16k/8k/4k x 16 MoBL ADM
Asynchronous Dual-Port Static RAM
Features
■
■
CYDMX256A16, CYDMX256B16
CYDMX128A16, CYDMX128B16
CYDMX064A16, CYDMX064B16
®
True dual-ported memory block that allow simultaneous
independent access
❐
One port with dedicated time multiplexed address and data
(ADM) interface
❐
One port configurable to standard SRAM or time multiplexed
address and data interface
16k/8k/4k × 16 memory configuration
High speed access
❐
65 ns or 90 ns ADM interface
❐
40 ns or 60 ns standard SRAM interface
Fully asynchronous operation
Port independent 1.8V, 2.5V, and 3.0V IOs
Ultra low operating power
❐
Active: I
CC
= 15 mA (typical) at 90 ns
❐
Active: I
CC
= 25 mA (typical) at 65 ns
❐
Standby: I
SB3
= 2
A
(typical)
Port independent power down
On-chip arbitration logic
Mailbox interrupt for port to port communication
Input Read and Output Drive registers
Upper byte and lower byte control
Small package: 6x6 mm, 100-ball Pb-free BGA
Industrial temperature range
■
■
■
■
■
■
■
■
■
■
■
Block Diagram
SFEN#
IRR/ODR
IRR1-IRR0 [note 2]
ODR4-ODR0
I/OL15-I/OL8
I/OL7-I/OL0
ADV#L
UB#L
LB#L
DataL<15..0>
Mux'ed
Address /
Data
I/O Control
Dual Ported
Memory Array
16k/8k/4k x 16
DataR<15..0>
Mux'ed
Address/
Data
I/O Control
I/OR15-I/OR8
I/OR7-I/OR0
ADV#R
UB#R
LB#R
A13-A0 [note 1]
AddrL<13..0>
AddrR<13..0>
Address
Decode
Address
Decode
MSEL
CS#L
OE#L
WE#L
BUSY#L
INT#L
Control Logic
CS#R
OE#R
WE#R
BUSY#R
INT#R
Notes
1. A13-A0 for CYDMX256A16 and CYDMX256B16; A12-A0 for CYDMX128A16 and CYDMX128B16; and A11-A0 for CYDMX064A16 and CYDMX064B16.
2. IRR1 and IRR2 not available for CYDMX256A16 and CYDMX256B16.
Cypress Semiconductor Corporation
Document #: 001-08090 Rev. *D
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised Sepember 15, 2010
CYDMX256A16, CYDMX256B16
CYDMX128A16, CYDMX128B16
CYDMX064A16, CYDMX064B16
Pin Configurations
Figure 1. 100-Ball 0.5 mm Pitch BGA (Top View)
1
A
B
C
D
E
A5
A3
A0
ODR4
VSS
2
A8
A4
A1
3
A11
A7
A2
4
UB#R
A9
A6
5
VSS
CE#R
LB#R
A10
VSS
VCC
OE#L
CE#L
VCC
ADV#L
5
6
ADV#R
WE#R
IRR1
[3]
A12
[4]
VSS
VSS
I/OL3
I/OL1
VSS
WE#L
6
7
I/OR15
OE#R
I/OR14
I/OR13
I/OR4
I/OR3
I/OL11
VDDIOL
I/OL4
I/OL0
7
8
I/OR12
VDDIOR
I/OR11
I/OR8
VDDIOR
I/OR0
I/OL12
MSEL
I/OL6
I/OL2
8
9
I/OR10
I/OR9
I/OR7
I/OR5
I/OR1
10
VSS
A
I/OR6
B
VSS
C
ODR2 BUSY#R INT#R
DNU
ODR1
DNU
DNU
DNU
DNU
2
ODR3
BUSY#L
DNU
DNU
DNU
DNU
3
INT#L
DNU
DNU
LB#L
IRR0
[5]
UB#L
4
I/O2R
D
VSS
E
F
SFEN#
G
H
J
K
ODR0
DNU
DNU
DNU
1
I/OL15 VDDIOL
F
I/OL14
DNU
I/OL8
I/OL5
9
I/OL13
G
I/OL10
H
I/OL9
I/OL7
10
J
K
.
Notes
3. This pin is A13 for CYDMX256A16 and CYDMX256B16.
4. This pin is DNU for CYDMX064A16 and CYDMX064B16.
5. This pin is DNU for CYDMX256A16 and CYDMX256B16.
6. DNU pins are “do not use” pins. No trace or power component can be connected to these pins.
Document #: 001-08090 Rev. *D
Page 2 of 22
CYDMX256A16, CYDMX256B16
CYDMX128A16, CYDMX128B16
CYDMX064A16, CYDMX064B16
Pin Definitions
Left Port
CS#L
WE#L
OE#L
Right Port
CS#R
WE#R
OE#R
A0–A13
MSEL
IOL0–IOL15
ADV#L
UB#L
LB#L
INT#L
BUSY#L
SFEN#
IRR0-IRR1
ODR0-ODR4
VCC
GND
VDDIOL
VDDIOR
DNU
IOR0–IOR15
ADV#R
UB#R
LB#R
INT#R
BUSY#R
Chip Select
Read/Write Enable
Output Enable
Address (A0–A11 for 4k device; A0–A12 for 8k device; A0–A13 for 16k device)
Right Port Interface Mode Select (0: Standard SRAM; 1: Address/Data Mux)
Address/Data Bus Input/Output
Address Latch Enable; ADV#R only use when R-port is in ADM mode
Upper Byte Select (IO8–IO15)
Lower Byte Select (IO0–IO7)
Interrupt Flag
Busy Flag
Special Function Enable Signal
Input Signals for Input Read Registers for CYDM128A16 and CYDMX064A16;
IRR0 is DNU and IRR1 is A13 for CYDMX256A16
Output Signals for Output Drive Registers; These are open drained outputs
Core Power Supply
Ground
Left Port IO Power Supply
Right Port IO Power Supply
No Connect; Do not connect trace or power component to these pins
connected to the V
DDIOL
and V
DDIOR
pins. The supported IO
standards are 1.8V and 2.5V LVCMOS and 3.0V LVTTL.
Description
Functional Description
The CYDMX256A16, CYDMX128A16, CYDMX064A16,
CYDMX256B16, CYDMX128B16, and CYDMX064B16 are low
power CMOS 16k/8k/4k x 16 dual-port static RAMs. The two
ports are: one dedicated time multiplexed address and data
(ADM) interface and one configurable standard SRAM or ADM
interface. The two ports permit independent, asynchronous read
and write access to any memory locations. Each port has
independent control pins: Chip Select (CS#), Write Enable
(WE#), and Output Enable (OE#). Two output flags are provided
on each port (BUSY# and INT#). BUSY# flag is triggered when
the port is trying to access the same memory location currently
being accessed by the other port. The Interrupt flag (INT#)
permits communication between ports or systems by means of
a mailbox. Power down feature is controlled independently on
each port by a Chip Select (CS#) pin.
The CYDMX256A16, CYDMX128A16, CYDMX064A16,
CYDMX256B16, CYDMX128B16, and CYDMX064B16 are
available in 100-ball 0.5-mm pitch Ball Grid Array (BGA)
packages. Application areas include interprocessor and multi-
processor designs, communications status buffering, and
dual-port video and graphics memory.
ADM Interface Read or Write Operation
This description is applicable to both the left ADM port and right
port configured as an ADM port.
Three control signals, ADV#, WE#, and CS# are used to perform
the read and write operations. Address signals are first applied
to the IO bus along with CS# LOW. The addresses are loaded
from the IO bus in response to the rising edge of the Address
Latch Enable (ADV#) signal. It is necessary to meet the setup
(t
AVDS
) and hold (t
AVDH
) times given in the AC specifications with
valid address information to properly latch the addresses.
After the address signals are latched in, a read operation is
issued when WE# stays HIGH. The IO bus becomes High-Z
when the address signals meet t
AVDH
. The read data is driven on
the IO bus t
OE
after the OE# is asserted LOW, and held until
t
HZOE
or t
HZCS
after the rising edge of OE# or CS#, whichever
comes first.
A write operation is issued when WE# is asserted LOW. The
write data is applied to the IO bus right after address meets the
hold time (t
AVDH
). And write data is written with the rising edge
of either WE# or CS#, whichever comes first, and meets data
setup (t
SD
) and hold (t
HD
) times.
Power Supply
The core voltage (V
CC
) can be 1.8V, 2.5V, or 3.0V, as long as it
is lower than or equal to the IO voltage. Each port operates on
independent IO voltages. This is determined by what is
Document #: 001-08090 Rev. *D
Page 3 of 22
CYDMX256A16, CYDMX256B16
CYDMX128A16, CYDMX128B16
CYDMX064A16, CYDMX064B16
Standard SRAM Interface Read or Write Operation
This description is applicable to the right access port configured
as standard SRAM port. Read and write operations with
standard SRAM interface configuration is the same as the ADM
port except addresses are presented on the A bus. Operation is
controlled by CS#, OE#, and WE#. A read operation is issued
when WE# is asserted HIGH. A write operation is issued when
WE# is asserted LOW. The IO bus is the destination for read data
and the source for write data when the read operation is issued.
However, write data must be driven to IO when the write
operation is issued.
resets when the owner reads the contents of its own mailbox.
The message written to the mailbox is user defined.
Each port reads the other port’s mailbox without resetting the
interrupt. The active state of the busy signal (to a port) prevents
the port from setting the interrupt to the winning port. Also, an
active busy to a port prevents that port from reading its own
mailbox and resetting the interrupt to it.
On power up, both interrupts are set by default. An initialization
program must be run to reset the interrupts.
If an application does not require message passing, do not
connect the interrupt pin to the processor’s interrupt request
input pin.
Byte Select Operation
The fundamental word size is 16 bits. Each word is broken up
into two 8-bit bytes. Each port has two active LOW byte enables:
UB# and LB#. Activating or deactivating the byte enables alters
the result of read and write operations to the port. During a write,
byte enable asserted HIGH inhibits the corresponding byte to be
updated in the addressed memory location. During a read, both
byte enables are inputs to the asynchronous output enable
control logic. When a byte enable is asserted HIGH, the corre-
sponding data byte is tri-stated. Subsequently, when the byte
enable is asserted LOW, the corresponding data byte is driven
with the read data.
Arbitration Logic
The CYDMX256A16, CYDMX128A16, CYDMX064A16,
CYDMX256B16, CYDMX128B16, and CYDMX064B16 provide
on-chip arbitration to resolve simultaneous memory location
access (collision). If both ports’ CS# signals are asserted and an
address match occurs within each other, the busy logic deter-
mines which port has access. If t
PS
is violated, one of the two
ports gains permission to the location, but it is not predictable
which port gets the permission. BUSY# is asserted t
BLA
after an
address match or t
BLC
after CS# is taken LOW.
Chip Select Operation
Each port has one active LOW chip select signal, CS#. CS# must
be asserted LOW for the port to be considered active. To issue
a valid read or write operation, the chip select input must be
asserted LOW throughout the read or write cycle. When CS# is
deasserted HIGH during a write, if t
WRL
, t
SD,
and t
HD
are not met,
the contents of the addressed location is not altered.
An automatic power down feature controlled by deactivating the
chip select (CS# HIGH) permits the on-chip circuitry of each port
to enter a very low standby power mode.
Input Read Register
The Input Read Register (IRR) feature is available only for
CYDMX128A16, CYDMX128B16, CYDMX064A16, and
CYDMX064B16 devices. When SFEN# = V
IL
, the IRR captures
the status of two external devices connected to the Input Read
pins (IRR0 and IRR1) to address location 0x0000. Address
0x0000 is not available for standard memory accesses when
SFEN# = V
IL.
When SFEN# = V
IH
, address 0x0000 is available
for normal memory accesses. Either port accesses the contents
of IRR with normal read operation from address 0x0000. During
reads from the IRR, IO<1:0> are valid bits and IO<15:2> are
don’t care. The IRR inputs are 1.8V and 2.5V LVCMOS or 3.0V
LVTTL, depending on the core voltage supply (V
CC
).
Output Enable Operation
Each port has one output enable signal, OE#. When OE# is
asserted HIGH, IO bus is tri-stated after t
HZOE
. When OE# is
asserted LOW, control of the IO bus is assumed by the
asynchronous output enable logic (the logic is controlled by
inputs WE#, CS#, UB#, and LB#).
Output Drive Register
The Output Drive Register (ODR) determines the state of up to
five external binary state devices by providing a path to V
SS
for
the external circuit. These outputs are open drain. The five
external devices operates at different voltages (1.5V
V
DDIO
3.5V) but the combined current cannot exceed 40 mA (8 mA
maximum for each external device). The status of the ODR bits
are set using standard write accesses from either port to address
0x0001 with a ‘1’ corresponding to on and ‘0’ corresponding to
off. The status of the ODR bits are read with a normal read
access to address 0x0001. When SFEN# = V
IL
, the ODR is
active and address 0x0001 is not available for memory
accesses. When SFEN# = V
IH
, the ODR is inactive and address
0x0001 is used for standard accesses. During reads and writes
to ODR, IO<4:0> are valid and IO<15:5> are don’t care.
Mailbox Interrupts
The upper two memory locations are used for message passing.
The highest memory location (0xFFF for CYDMX064A16 and
CYDMX064B16, 0x1FFF for CYDMX128A16 and CYDMX128B16,
and 0x3FFF for CYDMX256A16 and CYDMX256B16) is the
mailbox for the right port. The second highest memory location
(0xFFE for CYDMX064A16 and CYDMX064B16, 0x1FFE for
CYDMX128A16 and CYDMX128B16, and 0x3FFE for
CYDMX256A16 and CYDMX256B16) is the mailbox for the left
port. When one port writes to the opposite port’s mailbox, an
interrupt signal is generated to the opposite port. The interrupt
Document #: 001-08090 Rev. *D
Page 4 of 22
stm32/stm8
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
