CYW2315
Serial Input PLL with 1.2-GHz Prescaler
Features
• Operating voltage 2.7V to 5.5V
• Operating frequency: up to 1.2 GHz with prescaler
ratios of 64/65 and 128/129
• Lock detect feature
• Power-down mode
• 20-pin TSSOP (Thin Shrink Small Outline Package)
Applications
•
•
•
•
Wireless LAN
Wireless communication handsets
Base Stations
Microcells
CYW2315 PLL Block Diagram
GND (7)
V
CC
(5)
V
P
(4)
(6)
F
IN
(10)
Prescaler
64/65 or
128/129
Binary 7-Bit
Swallow Counter
Binary 11-Bit
Programmable Counter
fp
DO
Phase
Detector
Charge
Pump
(16)
BISW
(15)
FC
(20)
∅
r
(18)
∅
p
18-Bit
Latch
OSC_IN
OSC_OUT
(1)
14-Bit
Reference Counter
(3)
fr
(8)
LD
LE
(14)
Latch
Selector
15-Bit
Latch
DATA
(13)
Cntrl 19-Bit
Shift
Reg
Divider
Output
(fr/fp)
MUX
(17)
F
OUT
CLOCK
PWDN
(11)
(19)
Pin Configuration
OSC_IN
NC
OSC_OUT
V
P
V
CC
D
O
GND
LD
NC
F
IN
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
∅
r
PWDN
∅
p
F
out
BISW
FC
LE
DATA
NC
CLOCK
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134 •
408-943-2600
February 14, 2000, rev. **
CYW2315
R5
Q1
Crystal
Osc.
Input
1000p
R4
(1)
OSC
IN
∅
r
(20)
R6
Q2
(2)
NC
PWDN
(19)
(3)
OSC
OUT
100p
(18)
∅
p
R7
Q4
Q3
0.1µ
(4)
V
P
V
P
F
OUT
(17)
R8
R9
Vp
0.1µ
100p
(5)
V
CC
(6)
D
O
FC
V
CC
BISW
(16)
(15)
C1
C2
R2
C3
R3
(7)
GND
LE
(14)
(8)
LD
V
P
VCO*
18Ω
RF
OUT
V
CC
(13)
DATA
100k
LD
33k
18Ω
0.01
µF
10k
MMBT200
Lock
Detect
(9)
NC
NC
(12)
(10)
F
IN
CLOCK
(11)
18Ω
50Ω
100 pF
From
Controller
Figure 1. Application Diagram Example - CYW2315 1.2-GHz PLL
2
CYW2315
Pin Definitions
Pin Name
OSC_IN
NC
OSC_OUT
V
P
V
CC
D
O
GND
LD
NC
F
IN
CLOCK
NC
DATA
LE
F
C
BISW
F
OUT
∅
P
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Pin
Type
I
O
P
P
O
G
O
I
I
No Connect
Oscillator Output
Pin Description
Oscillator Input:
This input has a V
CC
/2 threshold and CMOS logic level sensitivity.
Charge Pump Rail Voltage:
This supply for charge pump. Must be > V
CC
.
Power Supply Connection for PLL:
When power is removed from V
CC
all latched
data is lost.
Charge Pump Output:
The phase detector gain is I
P
/2π. Sense polarity can be re-
versed by setting FC LOW (pin 15).
Analog and Digital Ground Connection:
This pin must be grounded.
Lock Detect Pin:
This output is HIGH with narrow LOW pulses when the loop is locked.
No Connect
Input to Prescaler:
Maximum frequency 1.2 GHz.
Data Clock Input:
One bit of data is loaded into the Shift Register on the rising edge
of this signal.
No Connect
Serial Data Input
Load Enable:
On the rising edge of this signal, the data stored in the Shift Register is
latched into the counters and configuration controls.
Phase Sense Control for Phase Detector with Internal Pull-up:
When pulled LOW,
the polarity of the Phase Detector is reversed.
Analog Switch Output:
Connects to output of charge pump when LE is HIGH.
Monitor Point for Phase Detector Input
External Charge Pump Output:
Open drain N-Channel FET, pull-up resistor required.
Power Down Pin with Internal Pull-up:
When pin is HIGH, device is in normal state.
When pin is LOW, device is in power-down mode. When device enters power-down
mode the charge pump is in the three-state condition.
External Change Pump:
(CMOS logic output).
I
I
I
O
O
O
I
PWDN
∅
R
20
O
3
CYW2315
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause per-
manent damage to the device. These represent a stress rating
Parameter
V
CC
or V
P
V
OUT
I
OUT
T
L
T
STG
Output Voltage
Output Current
Lead Temperature
Storage Temperature
Description
Power Supply Voltage
only. Operation of the device at these or any other conditions
above those specified in the operating sections of this specifi-
cation is not implied. Maximum conditions for extended peri-
ods may affect reliability.
Rating
–0.5 to +6.5
–0.5 to V
CC
+0.5
±15
+260
–55 to +150
Unit
V
V
mA
°C
°C
Handling Precautions
Devices should be transported and stored in antistatic con-
tainers.
These devices are static sensitive. Ensure that equipment and
personnel contacting the devices are properly grounded.
Cover workbenches with grounded conductive mats.
Always turn off power before adding or removing devices from
system.
Protect leads with a conductive sheet when handling or trans-
porting PC boards with devices.
If devices are removed from the moisture protective bags for
more than 36 hours, they should be baked at 85°C in a mois-
ture free environment for 24 hours prior to assembly in less
than 24 hours.
Recommended Operating Conditions
Parameter
V
CC
V
P
T
A
Description
Power Supply Voltage
Charge Pump Voltage
Operating Temperature
Ambient air at 0 CFM flow
Test Condition
Rating
2.7 to 5.5
V
CC
to +5.5
–40 to +85
Unit
V
V
°C
4
CYW2315
Electrical Characteristics:
V
CC
= 3.0V, V
P
= 3.0V, T
A
= –40°C to +85°C, Unless otherwise specified
Parameter
I
CC
I
PD
F
IN
F
OSC
PF
IN
V
OSC
I
IH
, I
IL
V
IH
V
IL
I
IH
I
IL
V
OH
V
OL
ID
O(SO)
ID
OH(SI)
∆ID
O
Description
Power Supply Current
Power-down Current
Maximum Operating
Frequency
Oscillator Input Frequency
Input Sensitivity
Oscillator Input Sensitivity
Oscillator Input Current
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
High Level Output Voltage
Low Level Output Voltage
ID
O
, Source Current
ID
O
High, Sink Current
ID
O
Charge Pump Sink and
Source Mismatch
Charge Pump Current
Variation vs. Temperature
Charge Pump High-
Impedance Leakage
Current
V
P
= 3.0V, VD
O
= V
P
/2
V
P
= 5.0V, VD
O
= V
P
/2
V
P
= 3.0V, VD
O
= V
P
/2
V
P
= 5.0V, VD
O
= V
P
/2
VD
O
= V
P
/2
[IID
O(SI)
I – IID
O(SO)
I]/
[1/2*{IID
O(SI)
]I+IID
O(SO)
I}]*100%
–40°C<T<85°C, V
DO
= V
P
/2
[1]
D
O
D
O
–3.2
–3.8
3.2
3.8
5
F
O
/LD
V
CC
= 5.0V
DATA,
CLOCK,
LE
No load on OSC_OUT
V
CC
= 2.7V
V
CC
= 5.5V
OSC_IN
Power-down, V
CC
= 3.0V
Test Condition
Pin
V
CC
V
CC
F
IN
OSC_IN
F
IN
–15
–10
0.5
–100
V
CC
* 0.8
V
CC
* 0.3
–10
–10
2.2
0.4
1
1
10
10
100
1.2
60
25
4
4
Min.
Typ.
4.5
6
100
Max.
Unit
mA
µA
GHz
MHz
MHz
dBm
dBm
V
P–P
µA
V
V
µA
µA
V
V
mA
mA
mA
mA
%
ID
O
vs T
ID
O-tri
5
±2.5
%
nA
Note:
1. ID
O
VS T; Charge pump current variation vs. temperature.
[IID
O(SI)@T
I – IID
O(SI)@25° C
I]/IID
O(SI)@25°C
I * 100% and
[IID
O(SO)@T
I – IID
O(SO)@25°C
I]/IID
O(SO)@25°C
I *100%.
5
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