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CY7C1312CV18
CY7C1314CV18
18-Mbit QDR
®
II SRAM 2-Word
Burst Architecture
Features
■
Configurations
CY7C1312CV18 – 1M x 18
CY7C1314CV18 – 512K x 36
Separate independent Read and Write Data Ports
❐
Supports concurrent transactions
250 MHz Clock for High Bandwidth
2-word Burst on all Accesses
Double Data Rate (DDR) Interfaces on both Read and Write
Ports (data transferred at 500 MHz) at 250 MHz
Two Input Clocks (K and K) for precise DDR Timing
❐
SRAM uses rising edges only
Two Input Clocks for Output Data (C and C) to minimize Clock
Skew and Flight Time mismatches
Echo Clocks (CQ and CQ) simplify Data Capture in High Speed
Systems
Single Multiplexed Address Input Bus latches Address Inputs
for both Read and Write Ports
Separate Port Selects for Depth Expansion
Synchronous internally Self-timed Writes
QDR
®
II operates with 1.5 Cycle Read Latency when Delay
Lock Loop (DLL) is enabled
Operates similar to a QDR I Device with one Cycle Read
Latency in DLL Off Mode
Available in x18, and x36 Configurations
Full Data Coherency, providing Most Current Data
Core V
DD
= 1.8V (±0.1V); IO V
DDQ
= 1.4V to V
DD
Available in 165-Ball FBGA Package (13 x 15 x 1.4 mm)
Offered in both Pb-free and non Pb-free Packages
Variable Drive HSTL Output Buffers
JTAG 1149.1 compatible Test Access Port
Delay Lock Loop (DLL) for accurate Data Placement
■
■
■
■
Functional Description
The CY7C1312CV18, and CY7C1314CV18 are 1.8V
Synchronous Pipelined SRAMs, equipped with QDR™-II archi-
tecture. QDR II architecture consists of two separate ports: the
read port and the write port to access the memory array. The
read port has data outputs to support read operations and the
write port has data inputs to support write operations. QDR II
architecture has separate data inputs and data outputs to
completely eliminate the need to “turn-around” the data bus
required with common I/O devices. Access to each port is
accomplished through a common address bus. The read
address is latched on the rising edge of the K clock and the write
address is latched on the rising edge of the K clock. Accesses to
the QDR II read and write ports are completely independent of
one another. To maximize data throughput, both read and write
ports are provided with DDR interfaces. Each address location
is associated with two 18-bit words (CY7C1312CV18), or 36-bit
words (CY7C1314CV18) that burst sequentially into or out of the
device. Because data can be transferred into and out of the
device on every rising edge of both input clocks (K and K and C
and C), memory bandwidth is maximized while simplifying
system design by eliminating bus “turn-arounds”.
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
Selection Guide
Description
Maximum Operating Frequency
Maximum Operating Current
x18
x36
250 MHz
250
800
900
200 MHz
200
675
750
167 MHz
167
600
650
Unit
MHz
mA
Cypress Semiconductor Corporation
Document #: 001-07164 Rev. *G
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised December 07, 2009
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CY7C1312CV18
CY7C1314CV18
Logic Block Diagram (CY7C1312CV18)
D
[17:0]
18
Write
Reg
Write
Reg
Read Add. Decode
Write Add. Decode
A
(18:0)
19
Address
Register
Address
Register
19
A
(18:0)
512K x 18 Array
512K x 18 Array
K
K
CLK
Gen.
RPS
Control
Logic
C
C
CQ
DOFF
Read Data Reg.
36
V
REF
WPS
BWS
[1:0]
Control
Logic
18
18
Reg.
Reg.
Reg. 18
18
18
CQ
Q
[17:0]
Logic Block Diagram (CY7C1314CV18)
D
[35:0]
36
Write
Reg
Write
Reg
Read Add. Decode
Write Add. Decode
A
(17:0)
18
Address
Register
Address
Register
18
A
(17:0)
256K x 36 Array
256K x 36 Array
K
K
CLK
Gen.
RPS
Control
Logic
C
C
CQ
DOFF
Read Data Reg.
72
V
REF
WPS
BWS
[3:0]
Control
Logic
36
36
Reg.
Reg.
Reg. 36
36
36
CQ
Q
[35:0]
Document #: 001-07164 Rev. *G
Page 2 of 25
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CY7C1312CV18
CY7C1314CV18
Contents
Features .............................................................................. 1
Configurations .................................................................... 1
Functional Description ....................................................... 1
Selection Guide .................................................................. 1
Logic Block Diagram (CY7C1312CV18) ............................ 2
Logic Block Diagram (CY7C1314CV18) ............................ 2
Contents .............................................................................. 3
Pin Configuration ............................................................... 4
165-Ball FBGA (13 x 15 x 1.4 mm) Pinout .................... 4
Pin Definitions .................................................................... 5
Functional Overview .......................................................... 7
Read Operations ........................................................... 7
Write Operations ........................................................... 7
Byte Write Operations ................................................... 7
Single Clock Mode ........................................................ 7
Concurrent Transactions ............................................... 7
Depth Expansion ........................................................... 7
Programmable Impedance ............................................ 8
Echo Clocks .................................................................. 8
DLL ................................................................................ 8
Application Example .......................................................... 8
Truth Table .......................................................................... 9
Write Cycle Descriptions ................................................... 9
Write Cycle Descriptions ................................................. 10
IEEE 1149.1 Serial Boundary Scan (JTAG) .................... 11
Disabling the JTAG Feature ........................................ 11
Test Access Port—Test Clock ..................................... 11
Test Mode Select (TMS) ............................................. 11
Test Data-In (TDI) ....................................................... 11
Test Data-Out (TDO) ................................................... 11
Performing a TAP Reset ............................................. 11
TAP Registers ............................................................. 11
TAP Instruction Set ..................................................... 11
TAP Controller State Diagram ......................................... 13
TAP Controller Block Diagram ........................................ 14
TAP Electrical Characteristics ........................................ 14
TAP AC Switching Characteristics ................................. 15
TAP Timing and Test Conditions .................................... 15
Identification Register Definitions .................................. 16
Scan Register Sizes ......................................................... 16
Instruction Codes ............................................................. 16
Boundary Scan Order ...................................................... 17
Power Up Sequence in QDR II SRAM ............................. 18
Power Up Sequence ................................................... 18
DLL Constraints .......................................................... 18
Maximum Ratings ............................................................. 19
Operating Range .............................................................. 19
Neutron Soft Error Immunity ........................................... 19
Electrical Characteristics ................................................ 19
DC Electrical Characteristics ....................................... 19
AC Electrical Characteristics ....................................... 20
Capacitance ...................................................................... 20
Thermal Resistance ......................................................... 20
Switching Characteristics ............................................... 21
Switching Waveforms ...................................................... 22
Ordering Information ....................................................... 23
Package Diagram ............................................................. 24
Sales, Solutions, and Legal Information ........................ 25
Worldwide Sales and Design Support ......................... 25
Document History Page ................................................... 25
Products ...................................................................... 25
Document #: 001-07164 Rev. *G
Page 3 of 25
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CY7C1312CV18
CY7C1314CV18
Pin Configuration
The pin configuration for CY7C1312CV18 and CY7C1314CV18 follow.
[1]
165-Ball FBGA (13 x 15 x 1.4 mm) Pinout
CY7C1312CV18 (1M x 18)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
Q9
NC
D11
NC
Q12
D13
V
REF
NC
NC
Q15
NC
D17
NC
TCK
3
D9
D10
Q10
Q11
D12
Q13
V
DDQ
D14
Q14
D15
D16
Q16
Q17
A
4
WPS
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
5
BWS
1
NC
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
K
K
A
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C
7
NC/288M
BWS
0
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
RPS
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
9
A
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
A
10
NC/72M
NC
Q7
NC
D6
NC
NC
V
REF
Q4
D3
NC
Q1
NC
D0
TMS
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
NC/144M NC/36M
CY7C1314CV18 (512K x 36)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
Q27
D27
D28
Q29
Q30
D30
DOFF
D31
Q32
Q33
D33
D34
Q35
TDO
2
Q18
Q28
D20
D29
Q21
D22
V
REF
Q31
D32
Q24
Q34
D26
D35
TCK
3
D18
D19
Q19
Q20
D21
Q22
V
DDQ
D23
Q23
D24
D25
Q25
Q26
A
4
WPS
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
5
BWS
2
BWS
3
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
K
K
A
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C
7
BWS
1
BWS
0
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
RPS
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
9
D17
D16
Q16
Q15
D14
Q13
V
DDQ
D12
Q12
D11
D10
Q10
Q9
A
10
Q17
Q7
D15
D6
Q14
D13
V
REF
Q4
D3
Q11
Q1
D9
D0
TMS
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
NC/288M NC/72M
NC/36M NC/144M
Note
1. NC/36M, NC/72M, NC/144M, and NC/288M are not connected to the die and can be tied to any voltage level.
Document #: 001-07164 Rev. *G
Page 4 of 25
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