353
CY7C1353
256Kx18 Flow-Through SRAM with NoBL™ Architecture
Features
• Pin compatible and functionally equivalent to ZBT™
devices MCM63Z819 and MT55L256L18F
• Supports 66-MHz bus operations with zero wait states
— Data is transferred on every clock
• Internally self-timed output buffer control to eliminate
the need to use OE
• Registered inputs for Flow-Through operation
• Byte Write capability
• 256K x 18 common I/O architecture
• Single 3.3V power supply
• Fast clock-to-output times
— 11.0 ns (for 66-MHz device)
— 12. 0 ns (for 50-MHz device)
— 14.0 ns (for 40-MHz device)
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed writes
• Asynchronous Output Enable
• JEDEC-standard 100 TQFP package
• Burst Capability—linear or interleaved burst order
• Low standby power
Functional Description
The CY7C1353 is a 3.3V, 256K by 18 Synchronous
Flow-Through Burst SRAM designed specifically to support
unlimited true back-to-back Read/Write operations without the
insertion of wait states. The CY7C1353 is equipped with the
advanced No Bus Latency™ (NoBL™) logic required to en-
able consecutive Read/Write operations with data being trans-
ferred on every clock cycle. This feature dramatically improves
the throughput of data through the SRAM, especially in sys-
tems that require frequent Write-Read transitions. The
CY7C1353 is pin/functionally compatible to ZBT™ SRAMs
MCM63Z819 and MT55L256L18F.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. The clock input is qualified by
the Clock Enable (CEN) signal, which when deasserted sus-
pends operation and extends the previous clock cycle. Maxi-
mum access delay from the clock rise is 11.0 ns (66-MHz de-
vice).
Write operations are controlled by the four Byte Write Select
(BWS
[1:0]
) and a Write Enable (WE) input. All writes are con-
ducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide for easy bank se-
lection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
Logic Block Diagram
CLK
D
Data-In REG.
CE Q
18
18
CONTROL
and WRITE
LOGIC
256KX18
MEMORY
ARRAY
18
DQ
[15:0]
DP
[1:0]
18
ADV/LD
A
[17:0]
CEN
CE1
CE 2
CE 3
WE
BWS [1:0]
Mode
18
OE
Selection Guide
7C1353-66
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
Commercial
Commercial
11.0
250 mA
5 mA
7C1353-50
12.0
200 mA
5 mA
7C1353-40
14.0
175 mA
5 mA
NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation.
ZBT is a trademark of Integrated Device Technology.
Cypress Semiconductor Corporation
Document #: 38-05081 Rev. **
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised September 4, 2001
CY7C1353
Pin Configuration
100-Pin TQFP
BWS
1
BWS
0
CE
1
CE
2
CE
3
V
DD
V
SS
CEN
CLK
WE
ADV/LD
OE
NC
NC
NC
A6
A7
NC
A
8
82
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
NC
NC
NC
V
DDQ
V
SS
NC
NC
DQ
8
DQ
9
V
SS
V
DDQ
DQ
10
DQ
11
V
SS
V
DD
V
DD
V
SS
DQ
12
DQ
13
V
DDQ
V
SS
DQ
14
DQ
15
DP
1
NC
V
SS
V
DDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
9
CY7C1353
A
17
NC
NC
V
DDQ
V
SS
NC
DP
0
DQ
7
DQ
6
V
SS
V
DDQ
DQ
5
DQ
4
V
SS
V
SS
V
DD
V
SS
DQ
3
DQ
2
V
DDQ
V
SS
DQ
1
DQ
0
NC
NC
V
SS
V
DDQ
NC
NC
NC
39
40
41
42
43
44
45
46
47
48
49
A
15
A
11
A
12
A
13
V
SS
DNU
V
DD
MODE
DNU
DNU
Document #: 38-05081 Rev. **
DNU
A
10
A
14
A
16
A
5
A
4
A
3
A
2
A
1
A
0
50
Page 2 of 13
CY7C1353
Pin Definitions
Pin Number
80, 50−44,
81−82, 99–
100, 32−37
94, 93
Name
A
[17:0]
I/O
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Description
Address Inputs used to select one of the 262,144 address locations. Sampled at
the rising edge of the CLK.
Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the
SRAM. Sampled on the rising edge of CLK. BWS
0
controls DQ
[7:0]
and DP
0
, BWS
1
controls DQ
[15:8]
and DP
1
. See Write Cycle Description table for details.
Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active
LOW. This signal must be asserted LOW to initiate a write sequence.
Advance/Load Input used to advance the on-chip address counter or load a new
address. When HIGH (and CEN is asserted LOW) the internal burst counter is
advanced. When LOW, a new address can be loaded into the device for an access.
After being deselected, ADV/LD should be driven LOW in order to load a new
address.
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified
with CEN. CLK is only recognized if CEN is active LOW.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE
2
, and CE
3
to select/deselect the device.
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE
1
and CE
3
to select/deselect the device.
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE and CE
2
to select/deselect the device.
Output Enable, active LOW. Combined with the synchronous logic block inside the
device to control the direction of the I/O pins. When LOW, the I/O pins are allowed
to behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act
as input data pins. OE is masked during the data portion of a write sequence,
during the first clock when emerging from a deselected state, when the device has
been deselected.
Clock Enable Input, active LOW. When asserted LOW the Clock signal is recog-
nized by the SRAM. When deasserted HIGH the Clock signal is masked. Since
deasserting CEN does not deselect the device, CEN can be used to extend the
previous cycle when required.
Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that
is triggered by the rising edge of CLK. As outputs, they deliver the data contained
in the memory location specified by A
[17:0]
during the previous clock rise of the
read cycle. The direction of the pins is controlled by OE and the internal control
logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH,
DQ
[15:0]
are placed in a three-state condition. The outputs are automatically
three-stated during the data portion of a write sequence, during the first clock when
emerging from a deselected state, and when the device is deselected, regardless
of the state of OE.
Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to
DQ
[15:0]
. During write sequences, DP
0
is controlled by BWS
0
and DP
1
is controlled
by BWS
1
.
Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved
burst order. Pulled LOW selects the linear burst order. MODE should not change
states during operation. When left floating MODE will default HIGH, to an inter-
leaved burst order.
Power supply inputs to the core of the device. Should be connected to 3.3V power
supply.
Power supply for the I/O circuitry. Should be connected to a 3.3V power supply.
Ground for the device. Should be connected to ground of the system.
BWS
[1:0]
88
85
WE
ADV/LD
89
98
97
92
86
CLK
CE
1
CE
2
CE
3
OE
Input-Clock
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Asynchronous
87
CEN
Input-
Synchronous
23−22,
DQ
[15:0]
19−18,
13−12, 9−8,
73−72,
69−68,
63−62, 59−58
I/O-
Synchronous
24, 74
DP
[1:0]
I/O-
Synchronous
Input
Strap pin
31
Mode
15, 16, 41, 65, V
DD
91
4, 11, 20, 27, V
DDQ
54, 61, 70, 77
5, 10, 14, 17, V
SS
21, 26, 40, 55,
60, 64,
66−67, 71,
76, 90
Power Supply
I/O Power
Supply
Ground
Document #: 38-05081 Rev. **
Page 3 of 13
CY7C1353
Pin Definitions
(continued)
Pin Number Name
1−3, 6−7, 25, NC
28−30,51−53,
56−57, 75,
78−79, 95−96
83, 84
NC
38, 39, 42, 43 DNU
I/O
-
Description
No Connects. These pins are not connected to the internal device.
-
-
No Connects. Reserved for address inputs for depth expansion. Pin 83 will be used
for 512K depth and pin 84 will be used for 1-Mb depth.
Do Not Use Pins. These pins should be left floating or tied to V
SS
.
must be driven LOW in order to load a new address into the
SRAM, as described in the Single Read Access section above.
The sequence of the burst counter is determined by the MODE
input signal. A LOW input on MODE selects a linear burst
mode, a HIGH selects an interleaved burst sequence. Both
burst counters use A0 and A1 in the burst sequence, and will
wrap around when incremented sufficiently. A HIGH input on
ADV/LD will increment the internal burst counter regardless of
the state of chip enable inputs or WE. WE is latched at the
beginning of a burst cycle. Therefore, the type of access (Read
or Write) is maintained throughout the burst sequence.
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE
1
, CE
2
,
and CE
3
are ALL asserted active, and (3) the write signal WE
is asserted LOW. The address presented to A
[17:0]
is loaded
into the Address Register. The write signals are latched into
the Control Logic block. The data lines are automatically
three-stated regardless of the state of the OE input signal. This
allows the external logic to present the data on DQ
[15:0]
and
DP
[1:0]
.
On the next clock rise the data presented to DQ
[15:0]
and
DP
[1:0]
(or a subset for byte write operations, see Write Cycle
Description table for details) inputs is latched into the device
and the write is complete. Additional accesses
(Read/Write/Deselect) can be initiated on this cycle.
The data written during the Write operation is controlled by
BWS
[1:0]
signals. The CY7C1353 provides byte write capabil-
ity that is described in the Write Cycle Description table. As-
serting the Write Enable input (WE) with the selected Byte
Write Select (BWS
[1:0]
) input will selectively write to only the
desired bytes. Bytes not selected during a byte write operation
will remain unaltered. A synchronous self-timed write mecha-
nism has been provided to simplify the write operations. Byte
write capability has been included in order to greatly simplify
Read/Modify/Write sequences, which can be reduced to sim-
ple byte write operations.
Because the CY7C1353 is a common I/O device, data should
not be driven into the device while the outputs are active. The
Output Enable (OE) can be deasserted HIGH before present-
ing data to the DQ
[15:0]
and DP
[1:0]
inputs. Doing so will
three-state the output drivers. As a safety precaution, DQ
[15:0]
and DP
[1:0]
.are automatically three-stated during the data por-
tion of a write cycle, regardless of the state of OE.
Burst Write Accesses
The CY7C1353 has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Write operations without reasserting the address inputs.
ADV/LD must be driven LOW in order to load the initial ad-
Page 4 of 13
Introduction
Functional Overview
The CY7C1353 is a Synchronous Flow-Through Burst SRAM
designed specifically to eliminate wait states during
Write-Read transitions. All synchronous inputs pass through
input registers controlled by the rising edge of the clock. The
clock signal is qualified with the Clock Enable input signal
(CEN). If CEN is HIGH, the clock signal is not recognized and
all internal states are maintained. All synchronous operations
are qualified with CEN. Maximum access delay from the clock
rise (t
CDV
) is 11.0 ns (66-MHz device).
Accesses can be initiated by asserting all three Chip Enables
(CE
1
, CE
2
, CE
3
) active at the rising edge of the clock. If clock
enable (CEN) is active LOW and ADV/LD is asserted LOW, the
address presented to the device will be latched. The access
can either be a read or write operation, depending on the sta-
tus of the Write Enable (WE). BWS
[1:0]
can be used to conduct
byte write operations.
Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self-timed write
circuitry.
Three synchronous Chip Enables (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) simplify depth expansion.
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD should be driven LOW once the device has been de-
selected in order to load a new address for the next operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE
1
, CE
2
,
and CE
3
are ALL asserted active, (3) the Write Enable input
signal WE is deasserted HIGH, and 4) ADV/LD is asserted
LOW. The address presented to the address inputs (A
[17:0]
) is
latched into the Address Register and presented to the mem-
ory core and control logic. The control logic determines that a
read access is in progress and allows the requested data to
propagate to the output buffers. The data is available within
11.0 ns (66-MHz device) provided OE is active LOW. After the
first clock of the read access the output buffers are controlled
by OE and the internal control logic. OE must be driven LOW
in order for the device to drive out the requested data. On the
subsequent clock, another operation (Read/Write/Deselect)
can be initiated. When the SRAM is deselected at clock rise
by one of the chip enable signals, its output will be three-stated
immediately.
Burst Read Accesses
The CY7C1353 has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Reads without reasserting the address inputs. ADV/LD
Document #: 38-05081 Rev. **
CY7C1353
dress, as described in the Single Write Access section above.
When ADV/LD is driven HIGH on the subsequent clock rise,
the chip enables (CE
1
, CE
2
, and CE
3
) and WE inputs are ig-
nored and the burst counter is incremented. The correct
BWS
[1:0]
inputs must be driven in each cycle of the burst write
in order to write the correct bytes of data.
Cycle Description Truth Table
[1, 2, 3, 4, 5, 6]
Operation
Deselected
Suspend
Begin Read
Begin Write
Burst READ
Operation
Address
used
External
-
External
External
Internal
CE
1
X
0
0
X
CEN
0
1
0
0
0
ADV/
LD
L
X
0
0
1
WE
X
X
1
0
X
BWS
x
X
X
X
Valid
X
CLK
L-H
L-H
L-H
L-H
L-H
Comments
I/Os three-state following next rec-
ognized clock.
Clock Ignored, all operations sus-
pended.
Address Latched.
Address Latched, data presented
two valid clocks later.
Burst Read Operation. Previous
access was a Read operation. Ad-
dresses incremented internally in
conjunction with the state of Mode.
Burst Write Operation. Previous
access was a Write operation. Ad-
dresses incremented internally in
conjunction with the state of Mode.
Bytes written are determined by
BWS
[1:0]
.
Burst WRITE
Operation
Internal
X
0
1
X
Valid
L-H
Interleaved Burst Sequence
First
Address
Ax+1, Ax
00
01
10
11
Second
Address
Ax+1, Ax
01
00
11
10
Third
Address
Ax+1, Ax
10
11
00
01
Fourth
Address
Ax+1, Ax
11
10
01
00
Linear Burst Sequence
First
Address
Ax+1, Ax
00
01
10
11
Second
Address
Ax+1, Ax
01
10
11
00
Third
Address
Ax+1, Ax
10
11
00
01
Fourth
Address
Ax+1, Ax
11
00
01
10
Write Cycle Description
[1, 2]
Function
Read
Write - No bytes written
Write Byte 0 - (DQ
[7:0]
and DP
0
)
Write Byte 1 - (DQ
[15:8]
and DP
1
)
Write All Bytes
WE
1
0
0
0
0
BWS
1
X
1
1
0
0
BWS
0
X
1
0
1
0
Notes:
1. X=Don’t Care”, 1=Logic HIGH, 0=Logic LOW, CE stands for ALL Chip Enables active. BWS
x
= 0 signifies at least one Byte Write Select is active, BWS
x
=
Valid signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.
2. Write is defined by WE and BWS
[1:0]
. See Write Cycle Description table for details.
3. The DQ and DP pins are controlled by the current cycle and the OE signal.
4. CEN=1 inserts wait states.
5. Device will power-up deselected and the I/Os in a three-state condition, regardless of OE.
6. OE assumed LOW.
Document #: 38-05081 Rev. **
Page 5 of 13
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