PRELIMINARY
CY7C1361V25
CY7C1363V25
256K x 36 / 512K x 18 Flowthrough SRAM
Features
• Supports 113-MHz bus operations
• 256K x 36 / 512K x 18 common I/O
• Fast clock-to-output times
— 7.5 ns (for 117-MHz device)
— 8.5 ns (for 100-MHz device)
— 10.0 ns (for 80-MHz device)
• Two-bit wrap-around counter supporting either inter-
leaved or linear burst sequences
• Separate processor and controller address strobes
provide direct interface with the processor and external
cache controller
• Synchronous self-timed writes
• Asynchronous output enable
• Single 2.5V Power supply
• JEDEC-standard pinout
• Available as a 100-pin TQFP or 119 BGA
• “ZZ” Sleep Mode option
Functional Description
The CY7C1361V25 and CY7C1363V25 are 2.5v, 256K x 36
and 512K x 18 synchronous-flowthrough SRAM designed to
interface with high-speed microprocessors with minimal glue
logic. Maximum access delay from the clock rise is 7.5 ns
(113-MHz device). A 2-bit on-chip wraparound burst counter
captures the first address in a burst sequence and automati-
cally increments the address for the rest of the burst access.
The CY7C1361V25/CY7C1363V25 supports either the inter-
leaved or linear burst sequences, selected by the MODE input
pin. A HIGH selects an interleaved burst sequence, while a
LOW selects a linear burst sequence. Burst accesses can be
initiated by asserting either the Processor Address Strobe
(ADSP) or the Controller Address Strobe (ADSC) at clock rise.
Address advancement through the burst sequence is con-
trolled by the ADV input. Byte write operations are qualified
with the Byte Write Select (BW
a,b,c,d
for CY7C1361V25 and
BW
a,b
for CY7C1363V25) inputs. A Global Write Enable (GW)
overrides all byte write inputs and writes data to all four bytes.
All writes are conducted with on-chip synchronous self-timed
write circuitry.
Three synchronous Chip Selects (CE
1
, CE
2
, CE
3
) and an
asynchronous output enable (OE) provide for easy bank selec-
tion and output three-state control.
Logic Block Diagram
CLK
ADV
A
x
GW
CE
1
CE2
CE3
BWE
7C1361V25 7C1363V25
BW
x
A
[17:0]
A
[18:0]
MODE
ADSP
DQ
a,b,c,d
DQ
a,b,c,d
ADSC
DP
a,b,c,d
DP
a,b
ZZ
BW
a,b
BW
a,b,c,d
OE
CONTROL
and WRITE
LOGIC
D
CE Data-In REG.
Q
256Kx36/
512Kx18
MEMORY
ARRAY
DQ
x
DP
x
A
X
DQ
X
DP
X
BW
X
Selection Guide
7C1361-133
7C1363-133
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
Shaded area contains advance information.
7C1361-113
7C1363-113
7.5
300
10
7C1361-100
7C1363-100
8.5
260
10
7C1361-80
7C1363-80
10.0
210
10
6.5
Commercial
350
10
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
August 5, 1999
PRELIMINARY
Pin Configurations
119-Ball BGA
CY7C1361V25
CY7C1363V25
CY7C1361 (256K x 36)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQc
DQc
V
DDQ
NC
DQb
V
DDQ
DQd
DQd
V
DDQ
DQd
DQd
NC
NC
V
DDQ
2
A
CE
2
A
DPc
DQc
DQc
DQc
DQc
V
DD
DQd
DQd
DQd
DQd
DPd
A
NC
TMS
3
A
A
A
V
SS
V
SS
V
SS
BWc
V
SS
NC
V
SS
BWd
V
SS
V
SS
V
SS
MODE
A
TDI
4
ADSP
ADSC
V
DD
NC
CE
1
OE
ADV
GW
DP0
CLK
NC
BWE
A1
A0
V
DD
A
TCK
5
A
A
A
V
SS
V
SS
V
SS
BWb
V
SS
NC
V
SS
BWa
V
SS
V
SS
V
SS
V
SS
A
TDO
6
A
A
A
DPb
DQb
DQb
DQb
DQb
V
DD
DQa
DQa
DQa
DQa
DPa
A
NC
NC
7
V
DDQ
NC
NC
DQb
DQb
V
DDQ
DQb
DQb
V
DDQ
DQa
DQa
V
DDQ
DQa
DQa
NC
ZZ
V
DDQ
CY7C1363 (512K x 18)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQb
NC
V
DDQ
NC
DQb
V
DDQ
NC
DQd
V
DDQ
DQb
NC
NC
NC
V
DDQ
2
A
CE
2
A
NC
DQb
NC
DQb
NC
V
DD
DQb
NC
DQb
NC
DPb
A
A
TMS
3
A
A
A
V
SS
V
SS
V
SS
BWb
V
SS
NC
V
SS
V
SS
V
SS
V
SS
V
SS
MODE
A
TDI
4
ADSP
ADSC
V
DD
NC
CE
1
OE
ADV
GW
DP0
CLK
NC
BWE
A1
A0
V
DD
NC
TCK
5
A
A
A
V
SS
V
SS
V
SS
V
SS
V
SS
NC
V
SS
BWa
V
SS
V
SS
V
SS
V
SS
A
TDO
6
A
A
A
DPa
NC
DQa
NC
DQb
V
DD
NC
DQa
NC
DQa
NC
A
A
NC
7
V
DDQ
NC
NC
NC
DQa
V
DDQ
DQa
NC
V
DDQ
DQa
NC
V
DDQ
NC
DQa
NC
ZZ
V
DDQ
2
PRELIMINARY
Pin Configurations
(continued)
100-Pin TQFP
CY7C1361V25
CY7C1363V25
A
A
CE
1
CE
2
BWd
BWc
BWb
BWa
CE
3
V
DD
V
SS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
DPc
DQc
DQc
V
DDQ
V
SSQ
DQc
DQc
DQc
DQc
V
SSQ
V
DDQ
DQc
DQc
V
SS
V
DD
NC
V
SS
DQd
DQd
V
DDQ
V
SSQ
DQd
DQd
DQd
DQd
V
SSQ
V
DDQ
DQd
DQd
DPd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1361
(256K X 36)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DPb
DQb
DQb
V
DDQ
V
SSQ
DQb
DQb
DQb
DQb
V
SSQ
V
DDQ
DQb
DQb
V
SS
NC
V
DD
ZZ
DQa
DQa
V
DDQ
V
SSQ
DQa
DQa
DQa
DQa
V
SSQ
V
DDQ
DQa
DQa
DPa
NC
NC
NC
V
DDQ
V
SSQ
NC
NC
DQb
DQb
V
SSQ
V
DDQ
DQb
DQb
V
SS
V
DD
NC
V
SS
DQb
DQb
V
DDQ
V
SSQ
DQb
DQb
DPb
NC
V
SSQ
V
DDQ
NC
NC
NC
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
CE
1
CE
2
NC
NC
BWb
BWa
CE
3
V
DD
V
SS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1363
(512K x 18)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
V
DDQ
V
SSQ
NC
DPa
DQa
DQa
V
SSQ
V
DDQ
DQa
DQa
V
SS
NC
V
DD
ZZ
DQa
DQa
V
DDQ
V
SSQ
DQa
DQa
NC
NC
V
SSQ
V
DDQ
NC
NC
NC
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
MODE
A
A
A
A
A
1
A
0
DNU
DNU
V
SS
V
DD
MODE
A
A
A
A
A
1
A
0
DNU
DNU
V
SS
V
DD
DNU
A
A
A
A
A
A
A
A
3
DNU
A
A
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
PRELIMINARY
Pin Definitions (100-Pin TQFP)
x18 Pin Location
37, 36, 32–25,
43–50, 80-82, 99,
100
93, 94
x36 Pin Location
37, 36, 32–35,
43–50, 81, 82, 99,
100
93, 94, 95, 96
Name
A0
A1
A
BWa
BWb
BWc
BWd
GW
I/O
Input-
Synchronous
CY7C1361V25
CY7C1363V25
Description
Address Inputs used to select one of the address loca-
tions. Sampled at the rising edge of the CLK if ADSP or
ADSC is active LOW, and CE
1
, CE
2
, and CE
3
are sam-
pled active. A
[1:0]
feed the 2-bit counter.
Byte Write Select Inputs, active LOW. Qualified with
BWE to conduct byte writes to the SRAM. Sampled on
the rising edge of CLK.
Global Write Enable Input, active LOW. When asserted
LOW on the rising edge of CLK, a global write is con-
ducted (ALL bytes are written, regardless of the values
on BW
a,b,c,d
and BWE).
Byte Write Enable Input, active LOW. Sampled on the
rising edge of CLK. This signal must be asserted LOW
to conduct a byte write.
Clock Input. Used to capture all synchronous inputs to
the device. Also used to increment the burst counter
when ADV is asserted LOW, during a burst operation.
Chip Enable 1 Input, active LOW. Sampled on the rising
edge of CLK. Used in conjunction with CE
2
and CE
3
to
select/deselect the device. ADSP is ignored if CE
1
is
HIGH.
Chip Enable 2 Input, active HIGH. Sampled on the rising
edge of CLK. Used in conjunction with CE
1
and CE
3
to
select/deselect the device.
Chip Enable 3 Input, active LOW. Sampled on the rising
edge of CLK. Used in conjunction with CE
1
and CE
2
to
select/deselect the device.
Output Enable, asynchronous input, active LOW. Con-
trols the direction of the I/O pins. When LOW, the I/O
pins behave as outputs. When deasserted HIGH, I/O
pins are three-stated, and act as input data pins. OE is
masked during the first clock of a read cycle when
emerging from a deselected state.
Advance Input signal, sampled on the rising edge of
CLK. When asserted, it automatically increments the
address in a burst cycle.
Address Strobe from Processor, sampled on the rising
edge of CLK. When asserted LOW, A is captured in the
address registers. A
[1:0]
are also loaded into the burst
counter. When ADSP and ADSC are both asserted, only
ADSP is recognized. ASDP is ignored when CE
1
is
deasserted HIGH.
Input-
Synchronous
88
88
Input-
Synchronous
87
87
BWE
Input-
Synchronous
Input-Clock
89
89
CLK
98
98
CE
1
Input-
Synchronous
97
97
CE
2
Input-
Synchronous
Input-
Synchronous
Input-
Asynchronous
92
92
CE
3
86
86
OE
83
83
ADV
Input-
Synchronous
Input-
Synchronous
84
84
ADSP
4
PRELIMINARY
Pin Definitions (100-Pin TQFP)
(continued)
x18 Pin Location
85
x36 Pin Location
85
Name
ADSC
I/O
Input-
Synchronous
CY7C1361V25
CY7C1363V25
Description
Address Strobe from Controller, sampled on the rising
edge of CLK. When asserted LOW, A
[x:0]
is captured in
the address registers. A
[1:0]
are also loaded into the
burst counter. When ADSP and ADSC are both assert-
ed, only ADSP is recognized.
Selects burst order. When tied to GND selects linear
burst sequence. When tied to V
DDQ
or left floating se-
lects interleaved burst sequence. This is a strap pin and
should remain static during device operation.
ZZ “sleep” Input. This active HIGH input places the de-
vice in a non-time critical “sleep” condition with data in-
tegrity preserved.
Bidirectional Data I/O lines. As inputs, they feed into an
on-chip data register that is triggered by the rising edge
of CLK. As outputs, they deliver the data contained in
the memory location specified by A during the previous
clock rise of the read cycle. The direction of the pins is
controlled by OE. When OE is asserted LOW, the pins
behave as outputs. When HIGH, DQx and DPx are
placed in a three-state condition.
Bidirectional Data I/O lines. As inputs, they feed into an
on-chip data register that is triggered by the rising edge
of CLK. As outputs, they deliver the data contained in
the memory location specified by A during the previous
clock rise of the read cycle. The direction of the pins is
controlled by OE. When OE is asserted LOW, the pins
behave as outputs. When HIGH, DQa–DQd and
DPa–DPd are placed in a three-state condition.
Power supply inputs to the core of the device. Should be
connected to 2.5V power supply.
Ground for the core of the device. Should be connected
to ground of the system.
Power supply for the I/O circuitry. Should be connected
to a 2.5V power supply.
Ground for the I/O circuitry. Should be connected to
ground of the system.
No Connects.
31
31
MODE
Input-
Static
64
64
ZZ
Input-
Asynchronous
I/O-
Synchronous
(a)58, 59, 62, 63,
68, 69, 72, 73
(b)8, 9, 12, 13, 18,
19, 22, 23
(a)52, 53, 56-59,
62, 63
(b)68, 69, 72–75,
78, 79
(c)2, 3, 6–9, 12, 13
(d)18, 19, 22-25,
28, 29
51, 80, 1, 30
DQa
DQb
DQc
DQd
74, 24
DPa
DPb
DPc
DPd
I/O-
Synchronous
15, 41, 65, 91
17, 40, 67, 90
4, 11, 20, 27, 54,
61, 70, 77
5, 10, 21, 26, 55,
60, 71, 76
1, 2, 3, 6, 7, 14, 16,
25, 28, 29, 30, 51,
52, 53, 56, 57, 66,
75, 78, 79, 95, 96
38, 39, 42
15, 41, 65, 91
17, 40, 67, 90
4, 11, 20, 27, 54,
61, 70, 77
5, 10, 21, 26, 55,
60, 71, 76
16, 66
V
DD
V
SS
V
DDQ
V
SSQ
NC
Power Supply
Ground
I/O Power
Supply
I/O Ground
-
38, 39
DNU
Do Not Use Pins. These pins should be left floating or
tied to V
SS
.
5
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