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CY7C1460AV25-250AC

产品描述ZBT SRAM, 1MX36, 2.6ns, CMOS, PQFP100
产品类别存储    存储   
文件大小382KB,共27页
制造商Cypress(赛普拉斯)
下载文档 详细参数 选型对比 全文预览

CY7C1460AV25-250AC概述

ZBT SRAM, 1MX36, 2.6ns, CMOS, PQFP100

CY7C1460AV25-250AC规格参数

参数名称属性值
是否无铅含铅
是否Rohs认证不符合
包装说明TQFP-100
Reach Compliance Codecompliant
最长访问时间2.6 ns
最大时钟频率 (fCLK)250 MHz
I/O 类型COMMON
JESD-30 代码R-PQFP-G100
JESD-609代码e0
长度20 mm
内存密度37748736 bit
内存集成电路类型ZBT SRAM
内存宽度36
功能数量1
端子数量100
字数1048576 words
字数代码1000000
工作模式SYNCHRONOUS
最高工作温度70 °C
最低工作温度
组织1MX36
输出特性3-STATE
封装主体材料PLASTIC/EPOXY
封装代码LQFP
封装等效代码QFP100,.63X.87
封装形状RECTANGULAR
封装形式FLATPACK, LOW PROFILE
并行/串行PARALLEL
峰值回流温度(摄氏度)NOT SPECIFIED
电源1.8/2.5,2.5 V
认证状态Not Qualified
座面最大高度1.6 mm
最大待机电流0.1 A
最小待机电流2.38 V
最大压摆率0.41 mA
最大供电电压 (Vsup)2.625 V
最小供电电压 (Vsup)2.375 V
标称供电电压 (Vsup)2.5 V
表面贴装YES
技术CMOS
温度等级COMMERCIAL
端子面层TIN LEAD
端子形式GULL WING
端子节距0.65 mm
端子位置QUAD
处于峰值回流温度下的最长时间NOT SPECIFIED
宽度14 mm
Base Number Matches1

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PRELIMINARY
CY7C1460AV25
CY7C1462AV25
CY7C1464AV25
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM
with NoBL™ Architecture
Features
• Pin-compatible and functionally equivalent to ZBT™
• Supports 250-MHz bus operations with zero wait states
— Available speed grades are 250, 200 and 167MHz
• Internally self-timed output buffer control to eliminate
the need to use asynchronous OE
• Fully registered (inputs and outputs) for pipelined
operation
• Byte Write capability
• Single 2.5V power supply
• 2.5V/1.8V I/O operation
• Fast clock-to-output times
— 2.6 ns (for 250-MHz device)
— 3.0 ns (for 200-MHz device)
— 3.4 ns (for 167-MHz device)
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed writes
• CY7C1460AV25 and CY7C1462AV25 available in 100
TQFP and 165 fBGA packages CY7C1464AV25 available
in 209-Ball fBGA package
• IEEE 1149.1 JTAG Boundary Scan
• Burst capability—linear or interleaved burst order
• “ZZ” Sleep Mode option and Stop Clock option
Functional Description
The CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 are
2.5V, 1M x 36 / 2M x 18 /Synchronous pipelined burst SRAMs
with No Bus Latency™ (NoBL™) logic, respectively. They are
designed to support unlimited true back-to-back Read/Write
operations with no wait states. The CY7C1460AV25/
CY7C1462AV25/CY7C1464AV25 are equipped with the
advanced (NoBL) logic required to enable consecutive
Read/Write operations with data being transferred on every
clock cycle. This feature dramatically improves the throughput
of data in systems that require frequent Write/Read transitions.
The CY7C1460AV25/ CY7C1462AV25/ CY7C1464AV25 are
pin compatible and functionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN) signal,
which when deasserted suspends operation and extends the
previous clock cycle. Write operations are controlled by the
Byte Write Selects (BW
a
–BW
h
for CY7C1464AV25,
BW
a
–BW
d
for CY7C1460AV25 and BW
a
–BW
b
for
CY7C1462AV25) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
Logic Block Diagram-CY7C1460AV25 (1M x 36)
A0, A1, A
MODE
CLK
CEN
ADDRESS
REGISTER 0
A1
A1'
D1
Q1
A0
A0'
BURST
D0
Q0
LOGIC
ADV/LD
C
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
C
ADV/LD
BW
a
BW
b
BW
c
BW
d
WE
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
E
DQs
DQP
a
DQP
b
DQP
c
DQP
d
E
INPUT
REGISTER 1
E
INPUT
REGISTER 0
E
OE
CE1
CE2
CE3
ZZ
READ LOGIC
SLEEP
CONTROL
Cypress Semiconductor Corporation
Document #: 38-05354 Rev. **
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised August 12, 2004

CY7C1460AV25-250AC相似产品对比

CY7C1460AV25-250AC CY7C1464AV25-225BGC CY7C1462AV25-200AC CY7C1462AV25-167AC CY7C1460AV25-225AC CY7C1460AV25-225BZC CY7C1462AV25-225BZC
描述 ZBT SRAM, 1MX36, 2.6ns, CMOS, PQFP100 ZBT SRAM, 512KX72, CMOS, PBGA209, ZBT SRAM, 2MX18, 3ns, CMOS, PQFP100 ZBT SRAM, 2MX18, 3.4ns, CMOS, PQFP100 ZBT SRAM, 1MX36, CMOS, PQFP100, ZBT SRAM, 1MX36, CMOS, PBGA165, ZBT SRAM, 2MX18, CMOS, PBGA165,
是否无铅 含铅 含铅 含铅 含铅 含铅 含铅 含铅
是否Rohs认证 不符合 不符合 不符合 不符合 不符合 不符合 不符合
包装说明 TQFP-100 FBGA-209 TQFP-100 TQFP-100 TQFP-100 FBGA-165 FBGA-165
Reach Compliance Code compliant compliant compliant compliant compliant compli compli
最大时钟频率 (fCLK) 250 MHz 225 MHz 200 MHz 167 MHz 225 MHz 225 MHz 225 MHz
I/O 类型 COMMON COMMON COMMON COMMON COMMON COMMON COMMON
JESD-30 代码 R-PQFP-G100 R-PBGA-B209 R-PQFP-G100 R-PQFP-G100 R-PQFP-G100 R-PBGA-B165 R-PBGA-B165
JESD-609代码 e0 e0 e0 e0 e0 e0 e0
长度 20 mm 22 mm 20 mm 20 mm 20 mm 17 mm 17 mm
内存密度 37748736 bit 37748736 bit 37748736 bit 37748736 bit 37748736 bit 37748736 bi 37748736 bi
内存集成电路类型 ZBT SRAM ZBT SRAM ZBT SRAM ZBT SRAM ZBT SRAM ZBT SRAM ZBT SRAM
内存宽度 36 72 18 18 36 36 18
功能数量 1 1 1 1 1 1 1
端子数量 100 209 100 100 100 165 165
字数 1048576 words 524288 words 2097152 words 2097152 words 1048576 words 1048576 words 2097152 words
字数代码 1000000 512000 2000000 2000000 1000000 1000000 2000000
工作模式 SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS
最高工作温度 70 °C 70 °C 70 °C 70 °C 70 °C 70 °C 70 °C
组织 1MX36 512KX72 2MX18 2MX18 1MX36 1MX36 2MX18
输出特性 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE
封装主体材料 PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
封装代码 LQFP BGA LQFP LQFP LQFP LBGA LBGA
封装等效代码 QFP100,.63X.87 BGA209,11X19,40 QFP100,.63X.87 QFP100,.63X.87 QFP100,.63X.87 BGA165,11X15,40 BGA165,11X15,40
封装形状 RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
封装形式 FLATPACK, LOW PROFILE GRID ARRAY FLATPACK, LOW PROFILE FLATPACK, LOW PROFILE FLATPACK, LOW PROFILE GRID ARRAY, LOW PROFILE GRID ARRAY, LOW PROFILE
并行/串行 PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL
峰值回流温度(摄氏度) NOT SPECIFIED 240 NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED
电源 1.8/2.5,2.5 V 1.8/2.5,2.5 V 1.8/2.5,2.5 V 1.8/2.5,2.5 V 1.8/2.5,2.5 V 1.8/2.5,2.5 V 1.8/2.5,2.5 V
认证状态 Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
座面最大高度 1.6 mm 1.96 mm 1.6 mm 1.6 mm 1.6 mm 1.4 mm 1.4 mm
最大待机电流 0.1 A 0.1 A 0.1 A 0.1 A 0.1 A 0.1 A 0.1 A
最小待机电流 2.38 V 2.38 V 2.38 V 2.38 V 2.38 V 2.38 V 2.38 V
最大供电电压 (Vsup) 2.625 V 2.625 V 2.625 V 2.625 V 2.625 V 2.625 V 2.625 V
最小供电电压 (Vsup) 2.375 V 2.375 V 2.375 V 2.375 V 2.375 V 2.375 V 2.375 V
标称供电电压 (Vsup) 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V
表面贴装 YES YES YES YES YES YES YES
技术 CMOS CMOS CMOS CMOS CMOS CMOS CMOS
温度等级 COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL
端子面层 TIN LEAD Tin/Lead (Sn/Pb) TIN LEAD TIN LEAD TIN LEAD Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb)
端子形式 GULL WING BALL GULL WING GULL WING GULL WING BALL BALL
端子节距 0.65 mm 1 mm 0.65 mm 0.65 mm 0.65 mm 1 mm 1 mm
端子位置 QUAD BOTTOM QUAD QUAD QUAD BOTTOM BOTTOM
处于峰值回流温度下的最长时间 NOT SPECIFIED 30 NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED
宽度 14 mm 14 mm 14 mm 14 mm 14 mm 15 mm 15 mm
Base Number Matches 1 1 1 1 - - -

 
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