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CY24713
Set-top Box Clock Generator with VCXO
Features
• Integrated phase-locked loop (PLL)
• Low-jitter, high-accuracy outputs
• VCXO with analog adjust
• 3.3V Operation
• 8-pin SOIC
Benefits
• High-performance PLL tailored for Set Top Box appli-
cations
• Meets critical timing requirements in complex system
designs
• Large ±150-ppm range, better linearity
• Meet industry standard voltage platforms
• Industry standard packaging saves on board space
Part Number
CY24713
Outputs
3
Input Frequency Range
27-MHz pullable crystal input
per Cypress specification
Output Frequencies
4.9152 MHz, 13.5 MHz, 27 MHz
Logic Block Diagram
Pin Configuration
Cypress Semiconductor Corporation
Document #: 38-07396 Rev. **
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Revised March 11, 2005
CY24713
Pin Description
Name
XIN
VDD
VCXO
VSS
CLK_B
CLK_A
CLK_C
XOUT
[1]
1
2
3
4
5
6
7
8
Number
Description
Reference Crystal Input
3.3V Voltage Supply
Input Analog Control for VCXO
Ground
13.5-MHz Clock Output
4.9152-MHz Clock Output
27-MHz Clock Output
Reference Crystal Output
Absolute Maximum Conditions
Parameter
V
DD
T
S
T
J
Storage
Description
Supply Voltage
Temperature
[2]
Junction Temperature
Digital Inputs
Digital Outputs referred to V
DD
Electrostatic Discharge
Analog Input
Min.
–0.5
–65
–
V
SS
– 0.3
V
SS
– 0.3
–
–0.5
Max.
7.0
125
125
V
DD
+ 0.3
V
DD
+ 0.3
2000
7.0
Unit
V
°C
°C
V
V
V
V
Pullable Crystal Specifications
Parameter
F
NOM
C
LNOM
R
1
R
3
/R
1
DL
F
3SEPHI
F
3SEPLO
C
0
C
0
/C
1
C
1
Description
Nominal crystal frequency
Nominal load capacitance
Equivalent series resistance (ESR)
Fundamental mode
Ratio of third overtone mode ESR to fundamen- Ratio used because typical
tal mode ESR
R
1
values are much less
than the maximum spec.
Crystal drive level
Third overtone separation from 3*F
NOM
Third overtone separation from 3*F
NOM
Crystal shunt capacitance
Ratio of shunt to motional capacitance
Crystal motional capacitance
No external series resistor
assumed
High side
Low side
Condition
Parallel resonance, funda-
mental mode, AT cut
Min.
–
–
–
3
Typ.
27
14
–
–
Max.
–
–
25
–
Unit
MHz
pF
Ω
–
300
–
–
180
14.4
0.5
–
–
–
–
18
2.0
–
–150
7
250
21.6
mW
ppm
ppm
pF
pF
Notes:
1. Float X
OUT
if X
IN
is externally driven.
2. Rated for 10 years
Document #: 38-07396 Rev. **
Page 2 of 6
CY24713
Recommended Operating Conditions
Parameter
V
DD
T
A
C
LOAD
t
PU
Description
Operating Voltage
Ambient Temperature
Max. Load Capacitance
Power-up time for all VDDs to
reach minimum specified voltage
(power ramps must be monotonic)
Min.
3.135
0
–
0.05
Typ.
3.3
–
–
–
Max.
3.465
70
15
500
Unit
V
°C
pF
ms
DC Electrical Characteristics
Parameter
I
OH
I
OL
C
IN
I
IZ
f
∆XO
V
VCXO
I
VDD
Description
Output High Current
Output Low Current
Input Capacitance
Input Leakage Current
VCXO pullability range
VCXO input range
Supply Current
Conditions
V
OH
= V
DD
– 0.5, V
DD
= 3.3V
V
OL
= 0.5, V
DD
= 3.3V
Min.
12
12
–
–
±150
0
–
Typ.
24
24
–
5
–
–
25
Max.
–
–
7
–
–
V
DD
30
Unit
mA
mA
pF
µA
ppm
V
mA
AC Electrical Characteristics
(V
DD
= 3.3V)
Parameter
[3]
DC
ER
0
EF
1
t
9
t
10
Description
Output Duty Cycle
Rising Edge Rate
Falling Edge Rate
Clock Jitter
PLL Lock Time
Conditions
Duty Cycle is defined in
Figure 1
50% of V
DD
Output Clock Edge Rate, Measured from 20%
to 80% of V
DD,
C
LOAD
= 15 pF
Figure 2.
Output Clock Edge Rate, Measured from 80%
to 20% of V
DD,
C
LOAD
= 15 pF
Figure 2.
Peak-Peak period jitter maximum absolute jitter
Min.
45
0.8
0.8
–
–
Typ.
50
1.4
1.4
200
–
Max.
55
–
–
250
3
Unit
%
V/ns
V/ns
ps
ms
Notes:
3. Not 100% tested
Document #: 38-07396 Rev. **
Page 3 of 6
CY24713
Test Circuit
V DD
0.1
µF
OUTPUTS
CLK out
C LOAD
GND
t1
t2
t3
80%
50%
t4
CLK
50%
CLK
20%
Figure 1. Duty Cycle Definition; DC = t2/t1
Figure 2. Rise and Fall Time Definitions: ER = 0.6 x V
DD
/t3,
EF = 0.6 x V
DD
/t4
Ordering Information
Ordering Code
CY24713SC
CY24713SCT
Lead-free
CY24713SXC
CY24713SXCT
8-pin SOIC
8-pin SOIC
Commercial
Commercial
3.3V
3.3V
Package Type
8-pin SOIC
8-pin SOIC
Operating Range
Commercial
Commercial
Operating Voltage
3.3V
3.3V
Document #: 38-07396 Rev. **
Page 4 of 6
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