can be internally generated as controlled by the Burst Advance
pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle. Write cycles can be one to
four bytes wide as controlled by the write control inputs.
Individual byte write allows individual byte to be written. WEL
controls DQ1–DQ8 and DQP1. WEH controls DQ9–DQ16 and
DQP2. WEL and WEH can be active only with BWE being
LOW. GW being LOW causes all bytes to be written.
The CY7C1324A operates from a +3.3V power supply and all
outputs operate on a +2.5V supply. All inputs and outputs are
JEDEC standard JESD8-5 compatible. The device is ideally
suited for 486, Pentium
, 680x0, and PowerPC™ systems
and for systems that benefit from a wide synchronous data
bus.
Functional Description
The Cypress Synchronous Burst SRAM family employs
high-speed, low-power CMOS designs using advanced
triple-layer polysilicon, double-layer metal technology. Each
memory cell consists of four transistors and two high-valued
resistors.
The CY7C1324A SRAM integrates 131,072 x 18 SRAM cells
with advanced synchronous peripheral circuitry and a two-bit
counter for internal burst operation. All synchronous inputs are
Logic Block Diagram
CLK
ADV
ADSC
ADSP
A
[16:0]
GW
BWE
BW
1
MODE
(A
0
,A
1
) 2
BURST Q
0
CE COUNTER
Q
1
CLR
Q
17
15
ADDRESS
CE REGISTER
D
15
17
128K X 18
MEMORY
ARRAY
D
Q
DQ[15:8]
BYTEWRITE
REGISTERS
Q
DQ[7:0]
BYTEWRITE
REGISTERS
D
BW
0
CE
1
CE
2
CE
3
D
ENABLE Q
CE REGISTER
CLK
18
18
INPUT
REGISTERS
CLK
OE
ZZ
SLEEP
CONTROL
DQ
[15:0]
DP
[1:0]
Note:
1. The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions, and timing diagrams for detailed information.
Cypress Semiconductor Corporation
Document #: 38-05325 Rev. *A
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised January 18, 2003
CY7C1324A
Selection Guide
7C1324A-117
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
7.5
370
10
7C1324A-100
8
320
10
Unit
ns
mA
mA
Pin Configurations
100-lead TQFP
OE
ADSC
BWS
1
BWS
0
ADSP
ADV
84
83
BWE
CE
1
CE
2
CE
3
V
DD
V
SS
CLK
GW
NC
NC
A6
A7
A
8
82
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
NC
NC
NC
V
DDQ
V
SS
NC
NC
DQ
8
DQ
9
V
SS
V
DDQ
DQ
10
DQ
11
NC
V
DD
NC
V
SS
DQ
12
DQ
13
V
DDQ
V
SS
DQ
14
DQ
15
DP
1
NC
V
SS
V
DDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
81
A
9
80
79
78
77
76
75
74
73
72
71
70
69
A
10
NC
NC
V
DDQ
V
SS
NC
DP
0
DQ
7
DQ
6
V
SS
V
DDQ
DQ
5
DQ
4
V
SS
NC
V
DD
ZZ
DQ
3
DQ
2
V
DDQ
V
SS
DQ
1
DQ
0
NC
NC
V
SS
V
DDQ
NC
NC
NC
CY7C1324A
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
BYTE0
BYTE1
MODE
A
5
A
4
A
3
A
2
A
1
A
0
A
15
A
16
DNU
DNU
A
11
A
12
A
13
V
SS
Document #: 38-05325 Rev. *A
DNU
DNU
V
DD
A
14
NC
Page 2 of 11
CY7C1324A
Pin Descriptions
QFP Pins
37, 36, 35, 34, 33,
32, 100, 99, 82, 81,
80, 48, 47, 46, 45,
44, 49
93, 94
Pin Name
A0–A16
Type
Input-
Synchronous
Description
Addresses:
These inputs are registered and must meet the set-up and hold
times around the rising edge of CLK. The burst counter generates internal
addresses associated with A0 and A1, during burst cycle and wait cycle.
Byte Write Enables:
A byte write enable is LOW for a Write cycle and HIGH
for a Read cycle. WEL controls DQ1–DQ8 and DQP1. WEH controls
DQ9–DQ16 and DQP2. Data I/O are high-impedance if either of these inputs
are LOW, conditioned by BWE being LOW.
Write Enable:
This active LOW input gates byte write operations and must
meet the set-up and hold times around the rising edge of CLK.
Global Write:
This active LOW input allows a full 18-bit Write to occur
independent of the BWE and WEn lines and must meet the set-up and hold
times around the rising edge of CLK.
Clock:
This signal registers the addresses, data, chip enables, write control
and burst control inputs on its rising edge. All synchronous inputs must meet
set-up and hold times around the clock’s rising edge.
Chip Enable:
This active LOW input is used to enable the device and to gate
ADSP.
Chip Enable:
This active LOW input is used to enable the device.
Chip Enable:
This active HIGH input is used to enable the device.
Output Enable:
This active LOW asynchronous input enables the data output
drivers.
Address Advance:
This active LOW input is used to control the internal burst
counter. A HIGH on this pin generates wait cycle (no address advance).
Address Status Processor:
This active LOW input, along with CE being
LOW, causes a new external address to be registered and a Read cycle is
initiated using the new address.
Address Status Controller:
This active LOW input causes device to be
deselected or selected along with new external address to be registered. A
Read or Write cycle is initiated depending upon write control inputs.
Mode:
This input selects the burst sequence. A LOW on this pin selects Linear
Burst. A NC or HIGH on this pin selects Interleaved Burst.
BWS
[1:0]
Input-
Synchronous
87
88
BWE
GW
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
input-
Synchronous
Input
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Static
89
CLK
98
92
97
86
83
84
CE
CE2
CE2
OE
ADV
ADSP
85
ADSC
31
64
MODE
ZZ
Input-
Snooze:
This active HIGH input puts the device in low power consumption
Asynchronous standby mode. For normal operation, this input has to be either LOW or NC
(No Connect).
Input/
Output
Input/
Output
Supply
Ground
I/O Supply
I/O Ground
–
Data Inputs/Outputs:
Low Byte is DQ1–DQ8. HIgh Byte is DQ9–DQ16. Input
data must meet setup and hold times around the rising edge of CLK.
Parity Inputs/Outputs:
DQP1 is parity bit for DQ1–DQ8 and DQP2 is parity
bit for DQ9–DQ16.
Power Supply:
+3.3V –5% and +10%
Ground:
GND
Output Buffer Supply:
+2.5V (from 2.375V to V
CC
)
Output Buffer Ground:
GND
No Connect:
These signals are not internally connected.
58, 59, 62, 63, 68, DQ1-DQ1
69, 72, 73, 8, 9, 12,
6
13, 18, 19, 22, 23
74, 24
15, 41,65, 91
17, 40, 67, 90
4, 11, 20, 27, 54,
61, 70, 77
5, 10, 21, 26, 55,
60, 71, 76
1–3, 6, 7, 14, 16,
25, 28-30, 38, 39,
42, 43, 51-53, 56,
57, 66, 75, 78, 79,
80, 95, 96
DQP1,
DQP2
V
CC
V
SS
V
CCQ
V
SSQ
NC
Document #: 38-05325 Rev. *A
Page 3 of 11
CY7C1324A
Burst Address Table (MODE = NC/V
CC
)
First
Address
(external)
A...A00
A...A01
A...A10
A...A11
Second
Address
(internal)
A...A01
A...A00
A...A11
A...A10
Third
Address
(internal)
A...A10
A...A11
A...A00
A...A01
Fourth
Address
(internal)
A...A11
A...A10
A...A01
A...A00
Burst Address Table (MODE = GND)
First
Address
(external)
A...A00
A...A01
A...A10
A...A11
Second
Address
(internal)
A...A01
A...A10
A...A11
A...A00
Third
Address
(internal)
A...A10
A...A11
A...A00
A...A01
Fourth
Address
(internal)
A...A11
A...A00
A...A01
A...A10
Truth Table
[2, 3, 4, 5, 6, 7, 8]
Operation
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
READ Cycle, Begin Burst
READ Cycle, Begin Burst
WRITE Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
WRITE Cycle, Continue Burst
WRITE Cycle, Continue Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
Address
Used
None
None
None
None
None
External
External
External
External
External
Next
Next
Next
Next
Next
Next
Current
Current
Current
Current
Current
Current
CE
H
L
L
L
L
L
L
L
L
L
X
X
H
H
X
H
X
X
H
H
X
H
CE2
X
X
H
X
H
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
CE2
X
L
X
L
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
ADSP
X
L
L
H
H
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
ADSC
L
X
X
L
L
X
X
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
ADV
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
H
H
H
H
H
H
WRITE
X
X
X
X
X
X
X
L
H
H
H
H
H
H
L
L
H
H
H
H
L
L
OE
X
X
X
X
X
L
H
X
L
H
L
H
L
H
X
X
L
H
L
H
X
X
CLK
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
DQ
High-Z
High-Z
High-Z
High-Z
High-Z
Q
High-Z
D
Q
High-Z
Q
High-Z
Q
High-Z
D
D
Q
High-Z
Q
High-Z
D
D
Notes:
2. X means “Don’t Care.” H means logic HIGH. L means logic LOW. WRITE = L means [BWE + WEL*WEH]*GW equals LOW. WRITE = H means [BWE +
WEL*WEH]*GW equals HIGH.
3. WEL enables write to DQ1–DQ8 and DQP1. WEH enables write to DQ9–DQ16 and DQP2.
4. All inputs except OE must meet set-up and hold times around the rising edge (LOW to HIGH) of CLK.
5. Suspending burst generates wait cycle.
6. For a write operation following a read operation, OE must be HIGH before the input data required set-up time plus High-Z time for OE and staying HIGH
throughout the input data hold time.
7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
8. ADSP LOW along with chip being selected always initiates a READ cycle at the L-H edge of CLK. A WRITE cycle can be performed by setting WRITE LOW
for the CLK L-H edge of the subsequent wait cycle. Refer to WRITE timing diagram for clarification.
Document #: 38-05325 Rev. *A
Page 4 of 11
CY7C1324A
Partial Truth Table for Read/Write
FUNCTION
READ
READ
WRITE one byte
WRITE all bytes
WRITE all bytes
GW
H
H
H
H
L
BWE
H
L
L
L
X
WEH
X
H
L
L
X
WEL
X
H
H
L
X
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines only, not tested.)
Voltage on V
CC
Supply Relative to V
SS
..........–0.5V to +4.6V
V
IN
......................................................... –0.5V to +V
CC
+0.5V
Storage Temperature (plastic) .................... –55°C to +125°C
Junction Temperature ............................................... +125°C
Power Dissipation.......................................................... 1.4W
Short Circuit Output Current ..................................... 100 mA
Operating Range
Range
Com’l
Ambient Temperature
[9]
0
°
C to
+70
°
C
V
CC
[10,11]
3.3V –5%/+10%
Electrical Characteristics
Over the Operating Range
[12]
Parameter
V
IHD
V
IH
V
Il
IL
I
IL
O
V
OH
V
OL
V
CC
V
CCQ
Parameter
I
CC
Input Low (Logic 0) Voltage
[13, 14]
Input Leakage Current
[15]
Output Leakage Current
Output High Voltage
[13, 16]
Output Low
I/O Supply
Voltage
[13, 16]
[13]
Description
Input High (Logic 1)
Voltage
[13, 14]
All other
Test Conditions
Data Inputs (DQxx)
Min.
1.7
1.7
–0.3
–2
–2
1.7
Max.
V
CC
+0.3
4.6
0.7
2
2
0.7
Unit
V
V
µA
µA
V
V
V
V
0V < V
IN
< V
CC
Output(s) disabled, 0V < V
OUT
< V
CC
I
OH
= –2.0 mA
I
OL
= 2.0 mA
Supply Voltage
3.135
2.375
-7
117 MHz
370
3.6
V
CC
-8
100 MHz
320
Description
Power Supply
Current:
Operating
[17, 18, 20]
CMOS
Standby
[18, 20]
TTL Standby
[18, 20]
Conditions
Device selected; all inputs < V
IL
or > V
IH
;
cycle time > t
KC
Min.; V
CC
= Max.; outputs
open
Device deselected; V
CC
= Max.; all inputs <
V
SS
+ 0.2 or > V
CC
– 0.2; all inputs static;
CLK frequency = 0
Device deselected; all inputs < V
IL
or > V
IH
;
all inputs static; V
CC
= Max.; CLK
frequency = 0
Device deselected; all inputs < V
IL
or > V
IH
;
V
CC
= Max.; CLK cycle time > t
KC
Min.
Typ.
150
Unit
mA
I
SB2
5
10
10
mA
I
SB3
10
20
20
mA
I
SB4
Clock
Running
[18, 20]
40
80
70
mA
Notes:
9. T
A
is the case temperature.
10. Please refer to waveform (c)
11. Power supply ramp up should be monotonic.
12. Values in table are associated with the operating frequencies listed.
13. All voltages referenced to V
SS
(GND).
14. Overshoot: V
IH
< +6.0V for t < t
KC
/2.
Undershoot:V
IL
< –2.0V for t < t
KC
/2.
15. MODE pin has an internal pull-up and ZZ pin has an internal pull-down. These two pins exhibit an input leakage current of ±30
µA.
16. AC I/O curves are available upon request.
17. I
CC
is given with no output current. I
CC
increases with greater output loading and faster cycle times.
18. “Device Deselected” means the device is in Power-down mode as defined in the truth table. “Device Selected” means the device is active.
19. Overshoot: VIH(AC) < VDD + 1.5V for t < tTCYC/2; undershoot: VIL(AC) < 0.5V for t < tTCYC/2; power-up: VIH < 2.6V and VDD < 2.4V and VDDQ < 1.4V for
t < 200 ms.
20. Typical values are measured at 3.3V, 25°C and 20-ns cycle time.
语音作为自然的人机接口，可以使车载导航系统实现更安全、更人性化的操作。通过国内外车载导航系统的功能对比可知，支持语音交互是车载导航系统的一个发展趋势。另外，市场信息服务公司J.D Power and Associates的调研数据也表明，56％的消费者更倾向于选择声控的导航系统。因此，开发车载语音导航系统是很有意义的。目前，国内已经具备开发车载语音导航系统的技术基础，特别是文语转换TTS技术...[详细]
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