851V25
52V25
ADVANCE INFORMATION
CY7C0851V25
CY7C0852V25
2.5V 64K/128K x 36
Sync Dual-Port Static RAM
Features
• True Dual-Ported memory cells that allow simultaneous
access of the same memory location
• Sync. Pipelined 4.5 Megabit devices
— 64K x 36 organization (CY7C0851V25)
•
•
•
•
— 128K x 36 organization (CY7C0852V25)
Pipelined output mode allows fast 100-MHz operation
0.18-micron CMOS for optimum speed/power
High-speed clock to data access: 5 ns (max.)
2.5V Low operating power
— Active = 150 mA (typical)
Functional Description
The CY7C0851V25/CY7C0852V25 is a 4.5-Megabit pipelined
synchronous true dual-port Static RAM. This is a high-speed,
low-power 2.5V CMOS dual-port static RAM. Two ports are
provided, permitting independent, simultaneous access for
reads from any location in memory. A particular port can write
to a certain location while the other port is reading that location
simultaneously. The result of writing to the same location by
more than one port at the same time is undefined. Registers
on control, address, and data lines allow for minimal set-up
and hold time.
During a read operation, data is registered for decreased cycle
time. Clock to data valid t
CD2
= 5 ns. Each port contains a burst
counter on the input address register. After externally loading
the counter with the initial address the counter will self-incre-
ment the address internally (more details to follow). The inter-
nal write pulse width is independent of the duration of the R/W
input signal. The internal write pulse is self-timed to allow the
shortest possible cycle times.
A HIGH on CE0 or LOW on CE1 for one clock cycle will power
down the internal circuitry to reduce the static power consump-
tion. One cycle is required with chip enables asserted to reac-
tivate the outputs.
Counter enable inputs are provided to stall the operation of the
address input and utilize the internal address generated by the
internal counter for fast interleaved memory applications. A
port’s burst counter is loaded when the port’s address strobe
(ADS) and (CNTEN) signals are LOW. When the port’s counter
enable (CNTEN) is asserted and the ADS is deasserted, the
address counter will increment on each LOW to HIGH transi-
tion of that port’s clock signal. This will read/write one word
from/into each successive address location until CNTEN is
deasserted. The counter can address the entire memory array
and will loop back to the start. Counter reset (CNTRST) is used
to reset the unmasked portion of the burst counter to 0s. A
counter-mask register is used to control the counter wrap. The
counter and mask register operations are described in more
detail in the following sections.
New features added to the CY7C0851V25/CY7C0852V25 in-
clude: readback of burst-counter internal address value on ad-
dress lines, counter-mask registers to control the counter
wrap-around and counter interrupt (CNTINT) flags, readback
of mask register value on address lines, retransmit functional-
ity, interrupt flags for message passing, JTAG for boundary
scan, and asynchronous Master Reset.
— Standby = 10 mA (typical)
• HSTL class 1 I/O (0.75 Vref)
• Counter wraparound control
— Internal mask register controls counter wraparound
— Counter-Interrupt flags to indicate wraparound
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— Memory Block Retransmit Operation
Counter readback on address lines
Mask register readback on address lines
Interrupt flags for message passing
Global Master reset
Width and Depth expansion capabilities
Dual Chip Enables on both ports for easy depth expan-
sion
Separate byte enables on both ports
Commercial and Industrial temperature ranges
IEEE 1149.1 JTAG boundary scan
172-ball BGA (1-mm pitch) (15 mm x 15 mm x 0.51 mm)
For the most recent information, visit the Cypress web site at www.cypress.com
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
October 17, 2000
ADVANCE INFORMATION
Pin Definitions
Left Port
A
0L
–A
16L
ADS
L
Right Port
A
0R
–A
16R
ADS
R
Address Inputs.
Description
CY7C0851V25
CY7C0852V25
Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW to
assert the part using the externally supplied address on Address Pins and to load this address
into the Burst Address Counter.
Active Low Chip Enable Input.
Active High Chip Enable Input.
Clock Signal. Maximum clock input rate is f
MAX
.
Counter Enable Input. Asserting this signal LOW increments the burst address counter of its
respective port on each rising edge of CLK. Increment is disabled if ADS or CNTRST are
asserted LOW.
Counter Reset Input. Asserting this signal LOW resets to zero the unmasked portion of the
burst address counter of its respective port. CNTRST is not disabled by asserting ADS or
CNTEN.
Address Counter Mask Register Enable Input. Asserting this signal LOW enables the access
to the mask register. When tied HIGH the mask register is not accessible and the address
counter operations are enabled based on the status of the counter control signals.
Output Enable Input. This asynchronous signal must be asserted LOW to enable the DQ data
pins during read operations.
Mailbox Interrupt Flag Output. Mailbox permits communications between ports. The upper two
memory locations can be used for message passing. INT
L
is asserted LOW when right port
writes to the mailbox location of left port and vice versa. Interrupt to a port is deasserted HIGH
when it reads the contents of its mailbox.
Counter Interrupt Output. This pin is asserted LOW when the unmasked portion of the counter
is incremented to all “1s.”
Read/Write Enable Input. Assert this pin LOW to write to, or HIGH to read from the dual-port
memory array.
Byte Select Inputs. Asserting these signals enables read and write operations to the corre-
sponding bytes of the memory array.
Master Reset Input. MRST is an asynchronous input and affects both ports. Asserting MRST
LOW performs all of the reset functions as described in the text. A MRST operation is required
at power-up.
JTAG Test Mode Select Input. It controls the advance of JTAG TAP state machine. State ma-
chine transitions occur on the rising edge of TCK.
JTAG Test Data Input. Data on the TDI input will be shifted serially into selected registers.
JTAG Test Clock Input.
JTAG Test Data Output. TDO transitions occur on the falling edge of TCK. TDO is normally
three-stated except when captured data is shifted out of the JTAG TAP
.
Ground Inputs (A: for address lines, Q: for data lines).
Power Inputs (A: for address lines, Q: for data lines).
CE0
L
CE1
L
CLK
L
CNTEN
L
CE0
R
CE1
R
CLK
R
CNTEN
R
CNTRST
L
CNTRST
R
CNT/MSK
L
CNT/MSK
R
DQ
0L
–DQ
35L
OE
L
INT
L
DQ
0R
–DQ
35R
Data Bus Input/Output.
OE
R
INT
R
CNTINT
L
R/W
L
B
0L
–B
3L
MRST
CNTINT
R
R/W
R
B
0L
–B
3L
TMS
TDI
TCK
TDO
V
SS
, V
SSA
, V
SSQ
V
DD
, V
DDA
, V
DDQ
5
模拟与混合信号
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