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CY14E064L
64 Kbit (8K x 8) nvSRAM
Features
■
■
■
■
■
■
■
■
■
■
■
■
Functional Description
The Cypress CY14E064L is a fast static RAM with a nonvol-
atile element in each memory cell. The embedded nonvolatile
elements incorporate QuantumTrap technology producing the
world’s most reliable nonvolatile memory. The SRAM provides
unlimited read and write cycles, while independent, nonvolatile
data resides in the highly reliable QuantumTrap cell. Data
transfers from the SRAM to the nonvolatile elements (the
STORE operation) takes place automatically at power down.
On power up, data is restored to the SRAM (the RECALL
operation) from the nonvolatile memory. Both the STORE and
RECALL operations are also available under software control.
A hardware STORE is initiated with the HSB pin.
25 ns and 45 ns access times
Hands off automatic STORE on power down with external
68 mF capacitor
STORE to QuantumTrap™ nonvolatile elements is initiated
by software, hardware, or AutoStore™ on power down
RECALL to SRAM initiated by software or power up
Unlimited READ, WRITE and RECALL cycles
10 mA typical ICC at 200 ns cycle time
1,000,000 STORE cycles to QuantumTrap
100 year data retention to QuantumTrap
Single 5V operation +10%
Commercial temperature
SOIC package
RoHS compliance
Logic Block Diagram
Quantum Trap
128 X 512
STORE
V
CC
V
CAP
A
5
A
7
A
8
A
9
A
11
A
12
ROW DECODER
A
6
POWER
CONTROL
STORE/
RECALL
CONTROL
STATIC RAM
ARRAY
128 X 512
RECALL
HSB
SOFTWARE
DETECT
COLUMN I/O
A
0
-
A
12
DQ
0
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
INPUT BUFFERS
DQ
1
COLUMN DEC
A
0
A
1
A
2
A
3
A
4
A
10
OE
CE
WE
Cypress Semiconductor Corporation
Document Number: 001-06543 Rev. *E
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised Apr 18, 2008
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CY14E064L
Pin Configurations
V
CAP
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
DQ0
DQ1
DQ2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
V
CC
WE
HSB
A
8
28-SOIC
Top View
(Not To Scale)
A
9
A
11
OE
A
10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
Pin Definitions
Pin Name
A
0
–A
12
WE
CE
OE
V
SS
V
CC
HSB
IO Type
Input
Input
Input
Input
Ground
Power Supply
Description
Address Inputs.
Used to select one of the 8,192 bytes of the nvSRAM.
Write Enable Input, Active LOW.
When selected LOW, writes data on the IO pins to the address
location latched by the falling edge of CE.
Chip Enable Input, Active LOW.
When LOW, selects the chip. When HIGH, deselects the chip.
Output Enable, Active LOW.
The active LOW OE input enables the data output buffers during read
cycles. Deasserting OE HIGH causes the IO pins to tri-state.
Ground for the Device.
The device is connected to ground of the system.
Power Supply Inputs to the Device.
DQ0-DQ7 Input or Output
Bidirectional Data IO lines.
Used as input or output lines depending on operation.
Input or Output
Hardware Store Busy (HSB).
When LOW, this output indicates a Hardware Store is in progress.
When pulled low external to the chip, it initiates a nonvolatile STORE operation. A weak internal pull
up resistor keeps this pin high if not connected (connection optional).
Power Supply
AutoStore Capacitor.
Supplies power to nvSRAM during power loss to store data from SRAM to
nonvolatile elements.
V
CAP
Document Number: 001-06543 Rev. *E
Page 2 of 17
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CY14E064L
Device Operation
The CY14E064L nvSRAM is made up of two functional compo-
nents paired in the same physical cell. These are an SRAM
memory cell and a nonvolatile QuantumTrap cell. The SRAM
memory cell operates as a standard fast static RAM. Data in the
SRAM is transferred to the nonvolatile cell (the STORE
operation) or from the nonvolatile cell to SRAM (the RECALL
operation). This unique architecture enables the storage and
recall of all cells in parallel. During the STORE and RECALL
operations, SRAM READ and WRITE operations are inhibited.
The CY14E064L supports unlimited reads and writes similar to
a typical SRAM. In addition, it provides unlimited RECALL opera-
tions from the nonvolatile cells and up to one million STORE
operations.
AutoStore Operation
The CY14E064L stores data to nvSRAM using one of three
storage operations:
1. Hardware store activated by HSB
2. Software store activated by an address sequence
3. AutoStore on device power down
AutoStore operation is a unique feature of QuantumTrap
technology and is enabled by default on the CY14E064L.
During normal operation, the device draws current from V
CC
to
charge a capacitor connected to the V
CAP
pin. This stored
charge is used by the chip to perform a single STORE operation.
If the voltage on the V
CC
pin drops below V
SWITCH
, the part
automatically disconnects the V
CAP
pin from V
CC
. A STORE
operation is initiated with power provided by the V
CAP
capacitor.
Figure 1
shows the proper connection of the storage capacitor
(V
CAP
) for automatic store operation. Refer to the
DC Electrical
Characteristics
on page 7 for the size of V
CAP
. The voltage on
the V
CAP
pin is driven to 5V by a charge pump internal to the chip.
A pull up is placed on WE to hold it inactive during power up.
Figure 1. AutoStore Mode
SRAM Read
The CY14E064L performs a READ cycle whenever CE and OE
are LOW while WE and HSB are HIGH. The address specified
on pins A
0–12
determines the 8,192 data bytes accessed. When
the READ is initiated by an address transition, the outputs are
valid after a delay of t
AA
(READ cycle 1). If the READ is initiated
by CE or OE, the outputs are valid at t
ACE
or at t
DOE
, whichever
is later (READ cycle 2). The data outputs repeatedly respond to
address changes within the t
AA
access time without the need for
transitions on any control input pins, and remains valid until
another address change or until CE or OE is brought HIGH, or
WE or HSB is brought LOW.
10k Ohm
SRAM Write
A WRITE cycle is performed whenever CE and WE are LOW and
HSB is HIGH. The address inputs are stable prior to entering the
WRITE cycle and must remain stable until either CE or WE goes
HIGH at the end of the cycle. The data on the common IO pins
I/O
0–7
are written into the memory if it is valid t
SD
, before the end
of a WE controlled WRITE or before the end of an CE controlled
WRITE. Keep OE HIGH during the entire WRITE cycle to avoid
data bus contention on common IO lines. If OE is left LOW,
internal circuitry turns off the output buffers t
HZWE
after WE goes
LOW.
1
28
27
26
68
U
F
6v, +20%
U
0.1 F
Bypass
14
15
Document Number: 001-06543 Rev. *E
10k Ohm
Page 3 of 17
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CY14E064L
In system power mode, both V
CC
and V
CAP
are connected to
the +5V power supply without the 68
μF
capacitor. In this
mode, the AutoStore function of the CY14E064L operates on
the stored system charge as power goes down. The user
must, however, guarantee that V
CC
does not drop below 3.6V
during the 10 ms STORE cycle.
If an automatic STORE on power loss is not required, then V
CC
is tied to ground and + 5V is applied to V
CAP
(Figure
2).
This
is the AutoStore Inhibit mode, where the AutoStore function is
disabled. If the CY14E064L is operated in this configuration,
references to V
CC
are changed to V
CAP
throughout this data
sheet. In this mode, STORE operations are triggered through
software control or the HSB pin. It is not permissible to change
between these three options at will. To reduce unnecessary
Figure 2. AutoStore Inhibit Mode
0.1
U
F
Bypass
place. If a WRITE is in progress when HSB is pulled LOW, it
allows a time, t
DELAY
to complete. However, any SRAM
WRITE cycles requested after HSB goes LOW are inhibited
until HSB returns HIGH.
The HSB pin is used to synchronize multiple CY14E064L while
using a single larger capacitor. To operate in this mode, the
HSB pin is connected together to the HSB pins from the other
CY14E064L. An external pull up resistor to +5V is required,
since HSB acts as an open drain pull down. The V
CAP
pins
from the other CY14E064L parts are tied together and share
a single capacitor. The capacitor size is scaled by the number
of devices connected to it. When any one of the CY14E064L
detects a power loss and asserts HSB, the common HSB pin
causes all parts to request a STORE cycle. (A STORE takes
place in those CY14E064L that are written since the last
nonvolatile cycle.)
During any STORE operation, regardless of how it is initiated,
the CY14E064L continues to drive the HSB pin LOW,
releasing it only when the STORE is complete. After
completing the STORE operation, the CY14E064L remains
disabled until the HSB pin returns HIGH.
If HSB is not used, it is left unconnected.
10k Ohm
1
28
27
26
10k Ohm
Hardware RECALL (Power Up)
During power up or after any low power condition (V
CC
<
V
SWITCH
), an internal RECALL request is latched. When V
CC
once again exceeds the sense voltage of V
SWITCH
, a RECALL
cycle is automatically initiated and takes t
HRECALL
to complete.
If the CY14E064L is in a WRITE state at the end of power up
RECALL, the SRAM data is corrupted. To help avoid this
situation, a 10 Kohm resistor is connected either between WE
and system V
CC
or between CE and system V
CC
.
Software STORE
14
15
nonvolatile stores, AutoStore and Hardware Store operations
are ignored, unless at least one WRITE operation has taken
place since the most recent STORE or RECALL cycle.
Software initiated STORE cycles are performed regardless of
whether a WRITE operation has taken place. The HSB signal
is monitored by the system to detect if an AutoStore cycle is in
progress.
Using a software address sequence, transfer the data from the
SRAM to the nonvolatile memory. The CY14E064L software
STORE cycle is initiated by executing sequential CE controlled
READ cycles from six specific address locations in exact
order. During the STORE cycle, an erase of the previous
nonvolatile data is first performed followed by a program of the
nonvolatile elements. When a STORE cycle is initiated, further
input and output are disabled until the cycle is completed.
Because a sequence of READs from specific addresses is
used for STORE initiation, it is important that no other READ
or WRITE accesses intervene in the sequence. If they
intervene, the sequence is aborted and no STORE or RECALL
takes place.
To initiate the software STORE cycle, the following READ
sequence is performed:
1. Read address 0x0000, Valid READ
2. Read address 0x1555, Valid READ
3. Read address 0x0AAA, Valid READ
4. Read address 0x1FFF, Valid READ
5. Read address 0x10F0, Valid READ
6. Read address 0x0F0F, Initiate STORE cycle
The software sequence is clocked with CE controlled READs
or OE controlled READs. When the sixth address in the
sequence is entered, the STORE cycle commences and the
chip is disabled. It is important that READ cycles and not
Page 4 of 17
Hardware STORE (HSB) Operation
The CY14E064L provides the HSB pin for controlling and
acknowledging the STORE operations. The HSB pin is used
to request a hardware STORE cycle. When the HSB pin is
driven LOW, the CY14E064L conditionally initiates a STORE
operation after t
DELAY
. An actual STORE cycle only begins if a
WRITE to the SRAM takes place since the last STORE or
RECALL cycle. The HSB pin also acts as an open drain driver
that is internally driven LOW to indicate a busy condition, while
the STORE (initiated by any means) is in progress.
SRAM READ and WRITE operations, that are in progress
when HSB is driven LOW by any means, are given time to
complete before the STORE operation is initiated. After HSB
goes LOW, the CY14E064L continues SRAM operations for
t
DELAY
. During t
DELAY
, multiple SRAM READ operations take
Document Number: 001-06543 Rev. *E
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