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CY7C1512V18
CY7C1514V18
72 Mbit QDR
®
II SRAM Two Word
Burst Architecture
Features
■
Functional Description
The CY7C1512V18, and CY7C1514V18 are 1.8V Synchronous
Pipelined SRAMs, equipped with QDR
®
II architecture. QDR II
architecture consists of two separate ports: the read port and the
write port to access the memory array. The read port has
dedicated data outputs to support read operations and the write
port has dedicated data inputs to support write operations. QDR
II architecture has separate data inputs and data outputs to
completely eliminate the need to “turnaround” the data bus that
exists with common IO devices. Access to each port is through
a common address bus. Addresses for read and write addresses
are latched on alternate rising edges of the input (K) clock.
Accesses to the QDR II read and write ports are completely
independent of one another. To maximize data throughput, both
read and write ports are equipped with DDR interfaces. Each
address location is associated with two 18 bit words
(CY7C1512V18), or 36 bit words (CY7C1514V18) that burst
sequentially into or out of the device. Because data can be trans-
ferred into and out of the device on every rising edge of both input
clocks (K and K and C and C), memory bandwidth is maximized
while simplifying system design by eliminating bus
“turnarounds”.
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self timed write circuitry.
Separate independent read and write data ports
❐
Supports concurrent transactions
250 MHz clock for High Bandwidth
2 word burst on all accesses
Double Data Rate (DDR) interfaces on both Read and Write
Ports (data transferred at 500 MHz) at 250 MHz
Two input clocks (K and K) for precise DDR timing
❐
SRAM uses rising edges only
Two Input Clocks for output data (C and C) to minimize Clock
Skew and Flight Time mismatches
Echo clocks (CQ and CQ) simplify Data Capture in High Speed
Systems
Single multiplexed address Input Bus latches Address Inputs
for both read and Write Ports
Separate port selects for Depth Expansion
Synchronous internally self timed writes
Available in x18, and x36 configurations
Full Data Coherency, providing most current data
Core V
DD
= 1.8V (±0.1V); IO V
DDQ
= 1.4V to V
DD
Available in 165-Ball FBGA package (15 x 17 x 1.4 mm)
Offered in both Pb-free and non Pb-free packages
Variable drive HSTL Output Buffers
JTAG 1149.1 compatible Test Access Port
Delay Lock Loop (DLL) for accurate data placement
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
Configurations
CY7C1512V18 – 4M x 18
CY7C1514V18 – 2M x 36
Selection Guide
Description
Maximum Operating Frequency
Maximum Operating Current
x18
x36
250 MHz
250
900
1100
200 MHz
200
800
900
167 MHz
167
750
800
Unit
MHz
mA
Cypress Semiconductor Corporation
Document #: 38-05489 Rev. *G
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised August 27, 2009
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CY7C1512V18
CY7C1514V18
Logic Block Diagram (CY7C1512V18)
D
[17:0]
18
Write
Reg
Write
Reg
Read Add. Decode
Write Add. Decode
A
(20:0)
21
Address
Register
Address
Register
21
A
(20:0)
2M x 18 Array
2M x 18 Array
K
K
CLK
Gen.
RPS
Control
Logic
C
C
CQ
DOFF
Read Data Reg.
36
V
REF
WPS
BWS
[1:0]
Control
Logic
18
18
Reg.
Reg.
Reg. 18
18
18
CQ
Q
[17:0]
Logic Block Diagram (CY7C1514V18)
D
[35:0]
36
Write
Reg
Write
Reg
Read Add. Decode
Write Add. Decode
A
(19:0)
20
Address
Register
Address
Register
20
A
(19:0)
1M x 36 Array
1M x 36 Array
K
K
CLK
Gen.
RPS
Control
Logic
C
C
CQ
DOFF
Read Data Reg.
72
V
REF
WPS
BWS
[3:0]
Control
Logic
36
36
Reg.
Reg.
Reg. 36
36
36
CQ
Q
[35:0]
Document #: 38-05489 Rev. *G
Page 2 of 26
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CY7C1512V18
CY7C1514V18
Pin Configuration
The pin configuration for CY7C1512V18, and CY7C1514V18 follow.
[1]
Figure 1. 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout
CY7C1512V18 (4M x 18)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
V
SS
/144M
3
A
D9
D10
Q10
Q11
D12
Q13
V
DDQ
D14
Q14
D15
D16
Q16
Q17
A
4
WPS
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
5
BWS
1
NC
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
K
K
A
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C
7
NC/288M
BWS
0
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
RPS
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
9
A
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
A
10
A
NC
Q7
NC
D6
NC
NC
V
REF
Q4
D3
NC
Q1
NC
D0
TMS
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
Q9
NC
D11
NC
Q12
D13
V
REF
NC
NC
Q15
NC
D17
NC
TCK
CY7C1514V18 (2M x 36)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
Q27
D27
D28
Q29
Q30
D30
DOFF
D31
Q32
Q33
D33
D34
Q35
TDO
2
V
SS
/288M
3
A
D18
D19
Q19
Q20
D21
Q22
V
DDQ
D23
Q23
D24
D25
Q25
Q26
A
4
WPS
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
5
BWS
2
BWS
3
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
K
K
A
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C
7
BWS
1
BWS
0
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
RPS
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
9
A
D17
D16
Q16
Q15
D14
Q13
V
DDQ
D12
Q12
D11
D10
Q10
Q9
A
10
V
SS
/144M
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
Q18
Q28
D20
D29
Q21
D22
V
REF
Q31
D32
Q24
Q34
D26
D35
TCK
Q17
Q7
D15
D6
Q14
D13
V
REF
Q4
D3
Q11
Q1
D9
D0
TMS
Note
1. V
SS
/144M and V
SS
/288M are not connected to the die and can be tied to any voltage level.
Document #: 38-05489 Rev. *G
Page 3 of 26
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CY7C1512V18
CY7C1514V18
Pin Definitions
Pin Name
D
[x:0]
I/O
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Pin Description
Data Input Signals.
Sampled on the rising edge of K and K clocks during valid write operations.
CY7C1512V18
−
D
[17:0]
CY7C1514V18
−
D
[35:0]
Write Port Select
−
Active LOW.
Sampled on the rising edge of the K clock. When asserted active, a
write operation is initiated. Deasserting deselects the write port. Deselecting the write port ignores D
[x:0]
.
Byte Write Select 0, 1, 2, and 3
−
Active LOW.
Sampled on the rising edge of the K and K clocks during
write operations. Used to select which byte is written into the device during the current portion of the write
operations. Bytes not written remain unaltered.
CY7C1512V18
−
BWS
0
controls D
[8:0]
and BWS
1
controls D
[17:9].
CY7C1514V18
−
BWS
0
controls D
[8:0]
, BWS
1
controls D
[17:9]
, BWS
2
controls D
[26:18]
and BWS
3
controls
D
[35:27].
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select
ignores the corresponding byte of data and it is not written into the device.
Address Inputs.
Sampled on the rising edge of the K (read address) and K (write address) clocks during
active read and write operations. These address inputs are multiplexed for both read and write operations.
Internally, the device is organized as 4M x 18 (2 arrays each of 2M x 18) for CY7C1512V18, and 2M x
36 (2 arrays each of 1M x 36) for CY7C1514V18. Therefore, only 21 address inputs are needed to access
the entire memory array of CY7C1512V18 and 20 address inputs for CY7C1514V18. These inputs are
ignored when the appropriate port is deselected.
Data Output Signals.
These pins drive out the requested data during a read operation. Valid data is
driven out on the rising edge of the C and C clocks during read operations, or K and K when in single
clock mode. When the read port is deselected, Q
[x:0]
are automatically tristated.
CY7C1512V18
−
Q
[17:0]
CY7C1514V18
−
Q
[35:0]
Read Port Select
−
Active LOW.
Sampled on the rising edge of positive input clock (K). When active, a
read operation is initiated. Deasserting deselects the read port. When deselected, the pending access is
allowed to complete and the output drivers are automatically tristated following the next rising edge of the
C clock. Each read access consists of a burst of four sequential transfers.
Positive Input Clock for Output Data.
C is used in conjunction with C to clock out the read data from
the device. Use C and C together to deskew the flight times of various devices on the board back to the
controller. See
Application Example
on page 7 for further details.
Negative Input Clock for Output Data.
C is used in conjunction with C to clock out the read data from
the device. Use C and C together to deskew the flight times of various devices on the board back to the
controller. See
Application Example
on page 7 for further details.
Positive Input Clock Input.
The rising edge of K is used to capture synchronous inputs to the device
and to drive out data through Q
[x:0]
when in single clock mode. All accesses are initiated on the rising
edge of K.
Negative Input Clock Input.
K is used to capture synchronous inputs being presented to the device and
to drive out data through Q
[x:0]
when in single clock mode.
CQ Referenced with Respect to C.
This is a free-running clock and is synchronized to the input clock
for output data (C) of the QDR II. In single clock mode, CQ is generated with respect to K. The timing for
the echo clocks is shown in
Switching Characteristics
on page 21.
CQ Referenced with Respect to C.
This is a free-running clock and is synchronized to the input clock
for output data (C) of the QDR II. In single clock mode, CQ is generated with respect to K. The timing for
the echo clocks is shown in the
Switching Characteristics
on page 21.
Output Impedance Matching Input.
This input is used to tune the device outputs to the system data bus
impedance. CQ, CQ, and Q
[x:0]
output impedance are set to 0.2 x RQ, where RQ is a resistor connected
between ZQ and ground. Alternatively, connect this pin directly to V
DDQ
, which enables the minimum
impedance mode. This pin cannot be connected directly to GND or left unconnected.
DLL Turn Off
−
Active LOW.
Connecting this pin to ground turns off the DLL inside the device. The timing
in the operation with the DLL turned off differs from those listed in this data sheet.
Page 4 of 26
WPS
BWS
0
,
BWS
1
,
BWS
2
,
BWS
3
A
Input-
Synchronous
Q
[x:0]
Output-
Synchronous
RPS
Input-
Synchronous
C
Input Clock
C
Input Clock
K
Input Clock
K
CQ
Input Clock
Echo Clock
CQ
Echo Clock
ZQ
Input
DOFF
Input
Document #: 38-05489 Rev. *G
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