CY7C1166V18, CY7C1177V18
CY7C1168V18, CY7C1170V18
18-Mbit DDR-II+ SRAM 2-Word Burst
Architecture (2.5 Cycle Read Latency)
Features
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Functional Description
The CY7C1166V18, CY7C1177V18, CY7C1168V18, and
CY7C1170V18 are 1.8V Synchronous Pipelined SRAMs
equipped with DDR-II+ architecture. The DDR-II+ consists of an
SRAM core with an advanced synchronous peripheral circuitry.
Addresses for read and write are latched on alternate rising
edges of the input (K) clock. Write data is registered on the rising
edges of both K and K. Read data is driven on the rising edges
of K and K. Each address location is associated with two 8-bit
words (CY7C1166V18), or 9-bit words (CY7C1177V18), or 18-bit
words (CY7C1168V18), or 36-bit words (CY7C1170V18) that
burst sequentially into or out of the device.
Asynchronous inputs include output impedance matching input
(ZQ). Synchronous data outputs (Q, sharing the same physical
pins as the data inputs D) are tightly matched to the two output
echo clocks CQ/CQ, eliminating the need for separately
capturing data from each individual DDR SRAM in the system
design.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
18 Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36)
300 MHz to 400 MHz clock for high bandwidth
2-Word burst for reducing address bus frequency
Double Data Rate (DDR) interfaces
(data transferred at 800 MHz) at 400 MHz
Read latency of 2.5 clock cycles
Two input clocks (K and K) for precise DDR timing
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SRAM uses rising edges only
Echo clocks (CQ and CQ) simplify data capture in high-speed
systems
Data valid pin (QVLD) to indicate valid data on the output
Synchronous internally self-timed writes
Core V
DD
= 1.8V ± 0.1V; IO V
DDQ
= 1.4V to V
DD[1]
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HSTL inputs and Variable drive HSTL output buffers
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Available in 165-Ball FBGA package (13 x 15 x 1.4 mm)
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Offered in both Pb-free and non Pb-free packages
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JTAG 1149.1-compatible test access port
Delay Lock Loop (DLL) for accurate data placement
Configurations
With Read Cycle Latency of 2.5 cycles:
CY7C1166V18 – 2M x 8
CY7C1177V18 – 2M x 9
CY7C1168V18 – 1M x 18
CY7C1170V18 – 512K x 36
Selection Guide
Description
Maximum Operating Frequency
Maximum Operating Current
400 MHz
400
1080
375 MHz
375
1020
333 MHz
333
920
300 MHz
300
850
Unit
MHz
mA
Note
1. The QDR consortium specification for V
DDQ
is 1.5V + 0.1V. The Cypress QDR devices exceed the QDR consortium specification and are capable of supporting
V
DDQ
= 1.4V to V
DD
.
Cypress Semiconductor Corporation
Document Number: 001-06620 Rev. *D
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198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised March 06, 2008
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