(except 2Q0 and 2Q1) in a LOW state (for PE/HD = H or M) – 2Q0, and
2Q1 may be used as the feedback signal to maintain phase lock. When
TEST is held at MID level and sOE# is HIGH, the nF[1:0] pins act as output
disable controls for individual banks when nF[1:0] = LL. Set sOE# LOW
for normal operation.
Selects Positive or Negative Edge Control, and High or Low output
Drive Strength.
When LOW/HIGH, the outputs are synchronized with the
negative/positive edge of the reference clock respectively. When at MID
level, the output drive strength is increased and the outputs synchronize
with the positive edge of the reference clock. See
Table 10
on page 5.
Selects Frequency and Phase of the Outputs.
See
Table 4, Table 5,
Table 6, Table 8,
and
Table 9
on page 4.
Selects VCO Operating Frequency Range.
See
Table 7
on page 4.
Four banks of two outputs.
See
Table 6
on page 4 for frequency
settings.
Selects Feedback Divider.
See
Table 3
on page 4.
Power down and Reference Divider Control.
When LOW, shuts off
entire chip. When at MID level, enables the reference divider. See
Table 2
for settings.
PLL Lock Indication Signal.
HIGH indicates lock, LOW indicates the
PLL is not locked, and outputs may not be synchronized to the input.
Power supply for Bank 4 Output Buffers.
See
Table 11
on page 5 for
supply level constraints.
Power supply for Bank 3 Output Buffers.
See
Table 11
on page 5 for
supply level constraints.
Power supply for Bank 1 and Bank 2 Output Buffers.
See
Table 11
on
page 5 for supply level constraints.
Power supply for the Internal Circuitry.
See
Table 11
on page 5 for
supply level constraints.
Ground
Table 2. Reference Divider Settings
PD#/DIV
R–Reference Divider
H
M
L
[4]
1
2
N/A
Description
I, PD LVTTL
4
PE/HD
I, PU 3-Level
34, 33, 36, 35, nF[1:0]
43, 42, 1, 44
41
26,27,20,21,
13,14,7,8
32, 31
3
FS
nQ[1:0]
DS[1:0]
PD#/DIV
I
I
O
I
3-Level
3-Level
LVTTL
3-Level
I, PU 3-Level
30
5,6
15,16
19,28,29
18,40
LOCK
O
LVTTL
V
DD
Q4
[2]
PWR Power
V
DD
Q3
[2]
PWR Power
V
DD
Q1
[2]
V
DD[2]
PWR Power
PWR Power
PWR Power
9-12, 22-25, 38 V
SS
Device Configuration
The outputs of the CY7B995 can be configured to run at
frequencies ranging from 6 MHz to 200 MHz. The feedback input
divider is controlled by the 3-level DS[0:1] pins as indicated in
Table 3
on page 4, and the reference input divider is controlled
by the 3-level PD#/DIV pin as indicated in
Table 2.
Notes
1. PD indicates an internal pull down and ‘PU’ indicates an internal pull up.
2. A bypass capacitor (0.1μF) must be placed as close as possible to each positive power pin (< 0.2”). If these bypass capacitors are not close to the pins, their high
frequency filtering characteristic is cancelled by the lead inductance of the traces.
3. When TEST = MID and sOE# = HIGH, PLL remains active with nF[1:0] = LL functioning as an output disable control for individual output banks. Skew selections
remain in effect unless nF[1:0] = LL.
4. When PD#/DIV = LOW, the device enters power down mode.
Document #: 38-07337 Rev. *D
Page 3 of 13
[+] Feedback
RoboClock
®
, CY7B995
Table 3. Feedback Divider Settings
DS[1:0] N-Feedback Input
Divider
LL
LM
LH
ML
MM
MH
HL
HM
HH
2
3
4
5
1
6
8
10
12
Permitted Output Divider
Connected to FB
1 or 2
1
1,2 or 4
1 or 2
1,2 or 4
1 or 2
1 or 2
1
1
Configuration
FB Input
Connected to
Output Frequency
1Q[0:1] and
2Q[0:1]
[6]
3Q[0:1]
4Q[0:1]
4Qn
(N / R) x M x (N / R) x (M / (N / R) x F
REF
F
REF
K) x F
REF
The 3-level FS control pin setting determines the nominal
operating frequency range of the divide-by-one outputs of the
device. The CY7B995 PLL operating frequency range that corre-
sponds to each FS level is given in
Table 7.
Table 7. Frequency Range Select
FS
L
M
H
PLL Frequency Range
24 to 50 MHz
48 to 100 MHz
96 to 200 MHz
In addition to the reference and feedback dividers, the CY7B995
includes output dividers on Bank3 and Bank4, which are
controlled by 3F[1:0] and 4F[1:0] as indicated in
Table 4
and
Table 5,
respectively.
Table 4. Output Divider Settings – Bank 3
3F[1:0]
LL
HH
Other
[5]
K - Bank3 Output Divider
2
4
1
Selectable output skew is in discrete increments of time units
(t
U
).The value of t
U
is determined by the FS setting and the
maximum nominal frequency. The equation used to determine
the t
U
value is: t
U
= 1 / (f
NOM
x MF)
where MF is a multiplication factor which is determined by the FS
setting as indicated in
Table 8.
Table 8. MF Calculation
FS
L
M
H
MF
32
16
8
f
NOM
at which t
U
is 1.0 ns (MHz)
31.25
62.5
125
Table 5. Output Divider Settings – Bank 4
4F[1:0]
LL
Other
[5]
M- Bank4 Output Divider
2
1
Table 9. Output Skew Settings
nF[1:0]
LL
[7]
LM
LH
4Q[0:1]
The divider settings and the FB input to any output connection
needed to produce various output frequencies are summarized
in
Table 6.
Table 6. Output Frequency Settings.
Configuration
FB Input
Connected to
Skew
(1Q[0:1],2Q[0:1])
–4t
U
–3t
U
–2t
U
–1t
U
Zero Skew
+1t
U
+2t
U
+3t
U
+4t
U
Skew
(3Q[0:1])
Divide By 2
–6t
U
–4t
U
–2t
U
Zero Skew
+2t
U
+4t
U
+6t
U
Divide By 4
Skew
(4Q[0:1])
Divide By 2
–6t
U
–4t
U
–2t
U
Zero Skew
+2t
U
+4t
U
+6t
U
Inverted
[8]
Output Frequency
1Q[0:1] and
2Q[0:1]
[6]
3Q[0:1]
ML
MM
MH
HL
HM
HH
1Qn or 2Qn
3Qn
(N / R) x F
REF
(N / R) x (1 / (N / R) x (1 /
K) x F
REF
M) x F
REF
(N / R) x K x (N / R) x F
REF
(N / R) x (K /
F
REF
M) x F
REF
Notes
5. These states are used to program the phase of the respective banks. See
Table 8
and
Table 9.
6. These outputs are undivided copies of the VCO clock. The formulas in this column can be used to calculate the VCO operating frequency (FNOM) at a given
reference frequency (FREF), and divider and feedback configuration. The user must select a configuration and a reference frequency that generates a VCO
frequency, and is within the range specified by FS pin. See
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