PSoC™ Mixed Signal Array
CY8C22113A and CY8C22213A
Preliminary Data Sheet
Features
■
Powerful Harvard Architecture Processor
❐
M8C Processor Speeds to 24 MHz
❐
Low Power at High Speed
❐
2.4 to 5.25 V Operating Voltage
❐
Industrial Temperature Range: -40°C to +85°C
■
Advanced Peripherals (PSoC Blocks)
❐
3 Rail-to-Rail Analog PSoC Blocks Provide:
- Up to 14-Bit ADCs
- Up to 9-Bit DACs
- Programmable Gain Amplifiers
- Programmable Filters and Comparators
❐
4 Digital PSoC Blocks Provide:
- 8- to 32-Bit Timers, Counters, and PWMs
- CRC and PRS Modules
- Full-Duplex UART
- SPI™ Masters or Slaves
- Connectable to all GPIO Pins
❐
Complex Peripherals by Combining Blocks
■
Precision, Programmable Clocking
❐
Internal ±2.5% 24/48 MHz Oscillator
❐
High-Accuracy 24 MHz with Optional 32.768
kHz Crystal and PLL
❐
Optional External Oscillator, up to 24 MHz
❐
Internal Oscillator for Watchdog and Sleep
■
Flexible On-Chip Memory
❐
2K Bytes Flash Program Storage 50,000
Erase/Write Cycles
❐
256 Bytes SRAM Data Storage
❐
In-System Serial Programming (ISSP™)
❐
Partial Flash Updates
❐
Flexible Protection Modes
❐
EEPROM Emulation in Flash
■
Programmable Pin Configurations
❐
25 mA Sink on all GPIO
❐
Pull up, Pull down, High Z, Strong, or Open
Drain Drive Modes on all GPIO
❐
Up to 8 Analog Inputs on GPIO
❐
One 30 mA Analog Outputs on GPIO
❐
Configurable Interrupt on all GPIO
■
Additional System Resources
❐
I
2
C™ Slave, Master, and Multi-Master to
400 kHz
❐
Watchdog and Sleep Timers
❐
User-Configurable Low Voltage Detection
❐
Integrated Supervisory Circuit
❐
On-Chip Precision Voltage Reference
■
Complete Development Tools
❐
Free Development Software
(PSoC™ Designer)
❐
Full-Featured, In-Circuit Emulator and
Programmer
❐
Full Speed Emulation
❐
Complex Breakpoint Structure
❐
128K Bytes Trace Memory
Port 1
Port 0
Analog
Drivers
PSoC™ Functional Overview
The PSoC™ family consists of many
Mixed Signal Array with
On-Chip Controller
devices. These devices are designed to
replace multiple traditional MCU-based system components
with one, low cost single-chip programmable device. PSoC
devices include configurable blocks of analog and digital logic,
as well as programmable interconnects. This architecture
allows the user to create customized peripheral configurations
that match the requirements of each individual application.
Additionally, a fast CPU, Flash program memory, SRAM data
memory, and configurable IO are included in a range of conve-
nient pinouts and packages.
The PSoC architecture, as illustrated on the left, is comprised of
four main areas: PSoC Core, Digital System, Analog System,
and System Resources. Configurable global busing allows all
the device resources to be combined into a complete custom
system. The PSoC CY8C22x13A family can have up to two IO
ports that connect to the global digital and analog interconnects,
providing access to 4 digital blocks and 3 analog blocks.
PSoC CORE
SYSTEM BUS
Global Digital Interconnect
Global Analog Interconnect
SRAM
256 Bytes
Interrupt
Controller
SROM
Flash 2K
Sleep and
Watchdog
CPU Core (M8C)
Multiple Clock Sources
(Includes IMO, ILO, PLL, and ECO)
DIGITAL SYSTEM
Digital
Block Array
(1 Row,
4 Blocks)
ANALOG SYSTEM
Analog
Block
Array
(1 Column,
3 Blocks)
Analog
Ref
Analog
Input
Muxing
The PSoC Core
The PSoC Core is a powerful engine that supports a rich fea-
ture set. The core includes a CPU, memory, clocks, and config-
urable GPIO (General Purpose IO).
The M8C CPU core is a powerful processor with speeds up to
24 MHz, providing a four MIPS 8-bit Harvard architecture micro-
Digital
Clocks
POR and LVD
Decimator
I
2
C
System Resets
Internal
Voltage
Ref.
SYSTEM RESOURCES
June 2004
© Cypress MicroSystems, Inc. 2004 — Document No. 38-12027 Rev. **
1
CY8C22x13A Preliminary Data Sheet
PSoC™ Overview
processor. The CPU utilizes an interrupt controller with 10 vec-
tors, to simplify programming of real time embedded events.
Program execution is timed and protected using the included
Sleep and Watch Dog Timers (WDT).
Memory encompasses 2 KB of Flash for program storage, 256
bytes of SRAM for data storage, and up to 2 KB of EEPROM
emulated using the Flash. Program Flash utilizes four protec-
tion levels on blocks of 64 bytes, allowing customized software
IP protection.
The PSoC device incorporates flexible internal clock genera-
tors, including a 24 MHz IMO (internal main oscillator) accurate
to 2.5% over temperature and voltage. The 24 MHz IMO can
also be doubled to 48 MHz for use by the digital system. A low
power 32 kHz ILO (internal low speed oscillator) is provided for
the Sleep timer and WDT. If crystal accuracy is desired, the
ECO (32.768 kHz external crystal oscillator) is available for use
as a Real Time Clock (RTC) and can optionally generate a crys-
tal-accurate 24 MHz system clock using a PLL. The clocks,
together with programmable clock dividers (as a System
Resource), provide the flexibility to integrate almost any timing
requirement into the PSoC device.
PSoC GPIOs provide connection to the CPU, digital and analog
resources of the device. Each pin’s drive mode may be selected
from eight options, allowing great flexibility in external interfac-
ing. Every pin also has the capability to generate a system inter-
rupt on high level, low level, and change from last read.
Digital peripheral configurations include those listed below.
■
■
■
■
■
■
■
■
■
■
PWMs (8 to 32 bit)
PWMs with Dead band (8 to 32 bit)
Counters (8 to 32 bit)
Timers (8 to 32 bit)
UART 8-bit with selectable parity (up to 1)
SPI master and slave (up to 1)
I2C slave and master (1 available as a System Resource)
Cyclical Redundancy Checker/Generator (8 to 32 bit)
IrDA (up to 1)
Pseudo Random Sequence Generators (8 to 32 bit)
The digital blocks can be connected to any GPIO through a
series of global buses that can route any signal to any pin. The
buses also allow for signal multiplexing and for performing logic
operations. This configurability frees your designs from the con-
straints of a fixed peripheral controller.
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This allows you the opti-
mum choice of system resources for your application. Family
resources are shown in the table titled
“PSoC Device Charac-
teristics” on page 3.
The Analog System
The Analog System is composed of 3 configurable blocks, each
comprised of an opamp circuit allowing the creation of complex
analog signal flows. Analog peripherals are very flexible and
can be customized to support specific application requirements.
Some of the more common PSoC analog functions (most avail-
able as user modules) are listed below.
■
The Digital System
The Digital System is composed of 4 digital PSoC blocks. Each
block is an 8-bit resource that can be used alone or combined
with other blocks to form 8, 16, 24, and 32-bit peripherals, which
are called user module references.
Port 1
Port 0
Analog-to-digital converters (one with 6- to 14-bit resolution,
selectable as Incremental, Delta Sigma, and SAR)
Filters (two pole band-pass, low-pass, and notch)
Amplifiers (one with selectable gain to 48x)
Comparators (one with 16 selectable thresholds)
DACs (one with 6- to 9-bit resolution)
Multiplying DACs (one with 6- to 9-bit resolution)
High current output drivers (one with 30 mA drive as a Core
Resource)
1.3V reference (as a System Resource)
Many other topologies possible
■
■
Digital Clocks
From Core
To System Bus
To Analog
System
■
■
■
DIGITAL SYSTEM
Digital PSoC Block Array
Row Input
Configuration
■
8
8
Row 0
DBB00
DBB01
DCB02
■
4
DCB03
4
8
Row Output
Configuration
■
8
GIE[7:0]
GIO[7:0]
Global Digital
Interconnect
GOE[7:0]
GOO[7:0]
Digital System Block Diagram
June 23, 2004
Document No. 38-12027 Rev. **
2
CY8C22x13A Preliminary Data Sheet
PSoC™ Overview
Analog blocks are arranged in a column of three, which
includes one CT (Continuous Time) and two SC (Switched
Capacitor) blocks, as shown in the figure below.
P0[7]
P0[5]
P0[3]
P0[1]
P0[6]
P0[4]
P0[2]
P0[0]
Additional System Resources
System Resources, some of which have been previously listed,
provide additional capability useful to complete systems. Addi-
tional resources include a decimator, low voltage detection, and
power on reset. Brief statements describing the merits of each
system resource are presented below.
■
Digital clock dividers provide three customizable clock fre-
quencies for use in applications. The clocks can be routed to
both the digital and analog systems. Additional clocks can be
generated using digital PSoC blocks as clock dividers.
The decimator provides a custom hardware filter for digital
signal processing applications including the creation of Delta
Sigma ADCs.
The I2C module provides 100 and 400 kHz communication
over two wires. Slave, master, and multi-master modes are
all supported.
Low Voltage Detection (LVD) interrupts can signal the appli-
cation of falling voltage levels, while the advanced POR
(Power On Reset) circuit eliminates the need for a system
supervisor.
An internal 1.3 voltage reference provides an absolute refer-
ence for the analog system, including ADCs and DACs.
■
■
■
■
Array Input Configuration
ACI0[1:0]
ACI1[1:0]
PSoC Device Characteristics
Depending on your PSoC device characteristics, the digital and
analog systems can have 16, 8, or 4 digital blocks and 12, 6, or
3 analog blocks. The following table lists the resources
available for specific PSoC device groups. The PSoC device
covered by this data sheet is shown in the last row of the table.
Block Array
ACB01
ASD11
ASC21
PSoC Device Characteristics
Analog
Columns
4
4
4
2
1
1
Analog
Outputs
Analog
Inputs
PSoC Part
Number
Analog
Blocks
12
12
12
6
3
3
Digital
Blocks
16
8
8
4
4
4
Digital
IO
up to
64
up to
44
up to
44
up to
24
up to
16
up to
16
Digital
Rows
4
2
2
1
1
1
CY8C29x66
12
12
12
12
8
8
4
4
4
2
1
1
Analog Reference
CY8C27x66
Interface to
Digital System
RefHi
RefLo
AGND
Reference
Generators
AGNDIn
RefIn
Bandgap
CY8C27x43
CY8C24x23
M8C Interface (Address Bus, Data Bus, Etc.)
CY8C22x13
CY8C22x13A
Analog System Block Diagram
June 23, 2004
Document No. 38-12027 Rev. **
3
CY8C22x13A Preliminary Data Sheet
PSoC™ Overview
Getting Started
The quickest path to understanding the PSoC silicon is by read-
ing this data sheet and using the PSoC Designer Integrated
Development Environment (IDE). This data sheet is an over-
view of the PSoC integrated circuit and presents specific pin,
register, and electrical specifications. For in-depth information,
along with detailed programming information, reference the
PSoC™ Mixed Signal Array Technical Reference Manual.
For up-to-date Ordering, Packaging, and Electrical Specification
information, reference the latest PSoC device data sheets on
the web at
http://www.cypress.com/psoc.
Development Tools
The Cypress MicroSystems PSoC Designer is a Microsoft
®
Windows-based, integrated development environment for the
Programmable System-on-Chip (PSoC) devices. The PSoC
Designer IDE and application runs on Windows 98, Windows
NT 4.0, Windows 2000, Windows Millennium (Me), or Windows
XP. (Reference the PSoC Designer Functional Flow diagram
below.)
PSoC Designer helps the customer to select an operating con-
figuration for the PSoC, write application code that uses the
PSoC, and debug the application. This system provides design
database management by project, an integrated debugger with
In-Circuit Emulator, in-system programming support, and the
CYASM macro assembler for the CPUs.
PSoC Designer also supports a high-level C language compiler
developed specifically for the devices in the family.
Development Kits
Development Kits are available from the following distributors:
Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store
at
http://www.onfulfillment.com/cypressstore/
contains develop-
ment kits, C compilers, and all accessories for PSoC develop-
ment. Click on
PSoC (Programmable System-on-Chip)
to view
a current list of available items.
Tele-Training
Free PSoC "Tele-training" is available for beginners and taught
by a live marketing or application engineer over the phone. Five
training classes are available to accelerate the learning curve
including introduction, designing, debugging, advanced design,
advanced analog, as well as application-specific classes cover-
ing topics like PSoC and the LIN bus. For days and times of the
tele-training, see
http://www.cypress.com/support/training.cfm.
PSoC
TM
Designer
Graphical Designer
Interface
Context
Sensitive
Help
Commands
Results
Importable
Design
Database
Device
Database
Application
Database
Project
Database
User
Modules
Library
PSoC
Configuration
Sheet
Consultants
Certified PSoC Consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC Consultant, go to the following Cypress support web site:
http://www.cypress.com/support/cypros.cfm.
PSoC
TM
Designer
Core
Engine
Technical Support
PSoC application engineers take pride in fast and accurate
response. They can be reached with a 4-hour guaranteed
response at
http://www.cypress.com/support/login.cfm.
Manufacturing
Information
File
Application Notes
A long list of application notes will assist you in every aspect of
your design effort. To locate the PSoC application notes, go to
http://www.cypress.com/design/results.cfm.
Emulation
Pod
In-Circuit
Emulator
Device
Programmer
PSoC Designer Subsystems
June 23, 2004
Document No. 38-12027 Rev. **
4
CY8C22x13A Preliminary Data Sheet
PSoC™ Overview
PSoC Designer Software Subsystems
Device Editor
The Device Editor subsystem allows the user to select different
onboard analog and digital components called user modules
using the PSoC blocks. Examples of user modules are ADCs,
DACs, Amplifiers, and Filters.
The device editor also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic configu-
ration allows for changing configurations at run time.
PSoC Designer sets up power-on initialization tables for
selected PSoC block configurations and creates source code
for an application framework. The framework contains software
to operate the selected components and, if the project uses
more than one operating configuration, contains routines to
switch between different sets of PSoC block configurations at
run time. PSoC Designer can print out a configuration sheet for
a given project configuration for use during application pro-
gramming in conjunction with the Device Data Sheet. Once the
framework is generated, the user can add application-specific
code to flesh out the framework. It’s also possible to change the
selected components and regenerate the framework.
Debugger
The PSoC Designer Debugger subsystem provides hardware
in-circuit emulation, allowing the designer to test the program in
a physical system while providing an internal view of the PSoC
device. Debugger commands allow the designer to read and
program and read and write data memory, read and write IO
registers, read and write CPU registers, set and clear break-
points, and provide program run, halt, and step control. The
debugger also allows the designer to create a trace buffer of
registers and memory locations of interest.
Online Help System
The online help system displays online, context-sensitive help
for the user. Designed for procedural and quick reference, each
functional subsystem has its own context-sensitive help. This
system also provides tutorials and links to FAQs and an Online
Support Forum to aid the designer in getting started.
Hardware Tools
In-Circuit Emulator
A low cost, high functionality ICE (In-Circuit Emulator) is avail-
able for development support. This hardware has the capability
to program single devices.
The emulator consists of a base unit that connects to the PC by
way of the parallel or USB port. The base unit is universal and
will operate with all PSoC devices. Emulation pods for each
device family are available separately. The emulation pod takes
the place of the PSoC device in the target board and performs
full speed (24 MHz) operation.
Design Browser
The Design Browser allows users to select and import precon-
figured designs into the user’s project. Users can easily browse
a catalog of preconfigured designs to facilitate time-to-design.
Examples provided in the tools include a 300-baud modem, LIN
Bus master and slave, fan controller, and magnetic card reader.
Application Editor
In the Application Editor you can edit your C language and
Assembly language source code. You can also assemble, com-
pile, link, and build.
Assembler.
The macro assembler allows the assembly code
to be merged seamlessly with C code. The link libraries auto-
matically use absolute addressing or can be compiled in relative
mode, and linked with other software modules to get absolute
addressing.
C Language Compiler.
A C language compiler is available
that supports Cypress MicroSystems’ PSoC family devices.
Even if you have never worked in the C language before, the
product quickly allows you to create complete C programs for
the PSoC family devices.
The embedded, optimizing C compiler provides all the features
of C tailored to the PSoC architecture. It comes complete with
embedded libraries providing port and bus operations, standard
keypad and display support, and extended math functionality.
PSoC Development Tool Kit
June 23, 2004
Document No. 38-12027 Rev. **
5
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