D ts e t
aa h e
R c e t r lc r nc
o h se Ee to is
Ma u a t r dCo o e t
n fc u e
mp n n s
R c e tr b a d d c mp n ns ae
o h se rn e
o oet r
ma ua trd u ig ete dewaes
n fcue sn i r i/ fr
h
p rh s d f m te oiia s p l r
uc a e r
o h r n l u pi s
g
e
o R c e tr waes rce td f m
r o h se
fr e rae r
o
te oiia I. Al rce t n ae
h
r nl P
g
l e rai s r
o
d n wi tea p o a o teOC
o e t h p rv l f h
h
M.
P r aetse u igoiia fcoy
at r e td sn r n la tr
s
g
ts p o rmso R c e tr e eo e
e t rga
r o h se d v lp d
ts s lt n t g aa te p o u t
e t oui s o u rne
o
rd c
me t o e c e teOC d t s e t
es r x e d h
M aa h e.
Qu l yOv riw
ai
t
e ve
• IO- 0 1
S 90
•A 92 cr ct n
S 1 0 et ai
i
o
• Qu l e Ma ua trr Ls (
ai d
n fcues it QML MI- R -
) LP F
385
53
•C a sQ Mitr
ls
lay
i
•C a sVS a eL v l
ls
p c ee
• Qu l e S p l r Ls o D sr uos( L )
ai d u pi s it f it b tr QS D
e
i
•R c e trsacic l u pir oD A a d
o h se i
r ia s p l t L n
t
e
me t aln u t a dD A sa d r s
es lid sr n L tn ad .
y
R c e tr lcrnc , L i c mmi e t
o h se Ee t is L C s o
o
tdo
t
s p ligp o u t ta s t f c so r x e t-
u pyn rd cs h t ai y u tme e p ca
s
t n fr u lya daee u loto eoiial
i s o q ai n r q a t h s r n l
o
t
g
y
s p l db id sr ma ua trr.
u pi
e yn ut
y n fcues
T eoiia ma ua trr d ts e t c o a yn ti d c me t e e t tep r r n e
h r n l n fcue’ aa h e a c mp n ig hs o u n r cs h ef ma c
g
s
o
a ds e ic t n o teR c e tr n fcue v rino ti d vc . o h se Ee t n
n p c ai s f h o h se ma ua trd eso f hs e ie R c e tr lcr -
o
o
isg aa te tep r r n eo i s mio d co p o u t t teoiia OE s e ic -
c u rne s h ef ma c ft e c n u tr rd cs o h r n l M p c a
o
s
g
t n .T pc lv le aefr eee c p r o e o l. eti mii m o ma i m rt g
i s ‘y ia’ au s r o rfrn e up s s ny C r n nmu
o
a
r xmu ai s
n
ma b b s do p o u t h rceiain d sg , i lt n o s mpetsig
y e a e n rd c c aa tr t , e in smuai , r a l e t .
z o
o
n
© 2 1 R cetr l t n s LC Al i t R sre 0 1 2 1
0 3 ohs E cr i , L . lRg s eevd 7 1 0 3
e e oc
h
T l r m r, l s v iw wrcl . m
o e n oe p ae it w . e c o
a
e
s
o ec
CY22050,
CY220501
One-PLL General Purpose
Flash Programmable Clock Generator
Features
■
■
■
■
■
■
■
■
Benefits
■
Integrated phase-locked loop (PLL)
Commercial and Industrial operation
Flash-programmable
Field-programmable
Low-skew, low-jitter, high-accuracy outputs
3.3V operation with 2.5V output option
16-Pin TSSOP package (CY22050)
16-Pin TSSOP package with NiPdAu lead finish (CY220501)
Internal PLL to generate six outputs up to 200 MHz. Able to
generate custom frequencies from an external reference
crystal or driven source.
Performance guaranteed for applications that require an
extended temperature range.
Reprogrammable technology allows easy customization, quick
turnaround on design changes and product performance
enhancements, and better inventory control. Parts can be
reprogrammed up to 100 times, reducing inventory of custom
parts and providing an easy method for upgrading existing
designs.
In-house programming of samples and prototype quantities is
available using the CY3672 FTG Development Kit. Production
quantities are available through Cypress’s value-added distri-
bution partners or by using third party programmers from BP
Microsystems, HiLo Systems, and others.
Industry standard packaging saves on board space.
Output Frequency Range
Specifications
Field-programmable
commercial temperature
Field-programmable
industrial temperature
Field-programmable
industrial temperature
NiPdAu lead finish
■
■
■
■
Table 1. Device Selection
Part Number
CY22050KFZXC
CY22050KFZXI
CY220501KFZXI
Outputs
6
6
6
Input Frequency Range
8 MHz–30 MHz (external crystal)
1 MHz–133 MHz (driven clock)
8 MHz–30 MHz (external crystal)
1 MHz–133 MHz (driven clock)
8 MHz–30 MHz (external crystal)
1 MHz–133 MHz (driven clock)
80 kHz–200 MHz (3.3V)
80 KHz–166.6 MHz (2.5V)
80 kHz–166.6 MHz (3.3V)
80 KHz–150 MHz (2.5V)
80 kHz–166.6 MHz (3.3V)
80 KHz–150 MHz (2.5V)
Logic Block Diagram
LCLK1
Divider
Bank 1
Output
Select
Matrix
VCO
P
PLL
Divider
Bank 2
CLK5
CLK6
LCLK2
LCLK3
LCLK4
XIN
XOUT
OSC.
Q
Φ
OE
VDD
AVDD AVSS
VSS
VDDL
VSSL
PWRDWN
Cypress Semiconductor Corporation
Document #: 38-07006 Rev. *G
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised July 24, 2009
[+] Feedback
CY22050,
CY220501
Pin Configuration
Figure 1. 16-Pin TSSOP
XIN
VDD
AVDD
PWRDWN
AVSS
VSSL
LCLK1
LCLK2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
XOUT
CLK6
CLK5
VSS
LCLK4
VDDL
OE
LCLK3
Table 2. Pin Definitions
Name
XIN
Pin Number
1
Description
Reference Input. Driven by a crystal (8 MHz–30 MHz) or external clock (1 MHz–133 MHz).
Programmable input load capacitors allow for maximum flexibility in selecting a crystal, based on
manufacturer, process, performance, or quality.
3.3V voltage supply
3.3V analog voltage supply
Power Down. When pin 4 is driven LOW, the CY22050 goes into shut down mode.
Analog ground
LCLK ground
Configurable clock output 1 at V
DDL
level (3.3V or 2.5V)
Configurable clock output 2 at V
DDL
level (3.3V or 2.5V)
Configurable clock output 3 at V
DDL
level (3.3V or 2.5V)
Output Enable. When pin 10 is driven LOW, all outputs are three-stated.
LCLK voltage supply (2.5V or 3.3V)
Configurable clock output 4 at V
DDL
level (3.3V or 2.5V)
Ground
Configurable clock output 5 (3.3V)
Configurable clock output 6 (3.3V)
Reference output
VDD
AVDD
PWRDWN
[1]
AVSS
VSSL
LCLK1
LCLK2
LCLK3
OE
[1]
VDDL
LCLK4
VSS
CLK5
CLK6
XOUT
[2]
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Notes
1. The CY22050 has no internal pull up or pull down resistors. PWRDWN and OE pins need to be driven as appropriate or tied to power or ground.
2. Float XOUT if XIN is driven by an external clock source.
Document #: 38-07006 Rev. *G
Page 2 of 10
[+] Feedback
CY22050,
CY220501
Functional Description
The CY22050 is the next-generation programmable FTG
(frequency timing generator) for use in networking,
telecommunication, datacom, and other general-purpose
applications. The CY22050 offers up to six configurable outputs
in a 16-pin TSSOP, running off a 3.3V power supply. The on-chip
reference oscillator is designed to run off an 8–30-MHz crystal,
or a 1–133-MHz external clock signal.
The CY22050 has a single PLL driving 6 programmable output
clocks. The output clocks are derived from the PLL or the
reference frequency (REF). Output post dividers are available for
either. Four of the outputs can be set as 3.3V or 2.5V, for use in
a wide variety of portable and low-power applications.
The CY220501 is the CY22050 with NiPdAu lead finish.
Applications
Controlling Jitter
Jitter is defined in many ways, including: phase noise, long-term
jitter, cycle-to-cycle jitter, period jitter, absolute jitter, and deter-
ministic jitter. These jitter terms are usually given in terms of rms,
peak-to-peak, or in the case of phase noise dBC/Hz with respect
to the fundamental frequency. Actual jitter is dependent on XIN
jitter and edge rate, number of active outputs, output
frequencies, V
DDL
(2.5V or 3.3V), temperature, and output load.
Power supply noise and clock output loading are two major
system sources of clock jitter. Power supply noise can be
mitigated by proper power supply decoupling (0.1-μF ceramic
cap) of the clock and ensuring a low-impedance ground to the
chip. Reducing capacitive clock output loading to a minimum
lowers current spikes on the clock edges and thus reduces jitter.
Reducing the total number of active outputs also reduce jitter in
a linear fashion. However, it is better to use two outputs to drive
two loads than one output to drive two loads.
The rate and magnitude that the PLL corrects the VCO frequency
is directly related to jitter performance. If the rate is too slow, then
long term jitter and phase noise is poor. Therefore, to improve
long-term jitter and phase noise, reducing Q to a minimum is
advisable. This technique increases the speed of the phase
frequency detector, which in turn drives the input voltage of the
VCO. In a similar manner, increasing P until the VCO is near its
maximum rated speed also decreases long term jitter and phase
noise. For example: input reference of 12 MHz; desired output
frequency of 33.3 MHz. One might arrive at the following
solution: Set Q = 3, P = 25, Post Div = 3. However, the best jitter
results are Q = 2, P = 50, Post Div = 9.
For additional information, refer to the application note, “Jitter in
PLL-based Systems: Causes, Effects, and Solutions,” available
at
http://www.cypress.com
(click on “Application Notes”), or
contact your local Cypress Field Applications Engineer.
Field Programming the CY22050F
The CY22050 is programmed at the package level, that is, in a
programmer socket, prior to installation on a PCB. The CY22050
is flash-technology based, so the parts can be reprogrammed up
to 100 times. This allows for fast and easy design changes and
product updates, and eliminates any issues with old and
out-of-date inventory.
Samples and small prototype quantities can be programmed on
the CY3672 programmer. Cypress’s value-added distribution
partners and third-party programming systems from BP Micro-
systems, HiLo Systems, and others are available for
large-production quantities.
CyberClocks™ Software
CyberClocks is an easy-to-use software application that allows
the user to custom-configure the CY22050. Within CyberClocks,
select the CyClocksRT
™
tool. Users can specify the REF, PLL
frequency, output frequencies and/or post-dividers, and different
functional options. CyClocksRT outputs an industry-standard
JEDEC file used for programming the CY22050.
CyClocksRT can be downloaded free of charge from the
Cypress website at
http://www.cypress.com.
Install and run it on
any PC running the Windows operating system.
CY3672 Development Kit
The Cypress CY3672 Development Kit comes complete with
everything needed to design with the CY22050 and program
samples and small prototype quantities. The kit comes with the
latest version of CyClocksRT and a small portable programmer
that connects to a PC for on-the-fly programming of custom
frequencies.
The JEDEC file output of CyClocksRT can be downloaded to the
portable programmer for small-volume programming, or for use
with a production programming system for larger volumes.
Document #: 38-07006 Rev. *G
Page 3 of 10
[+] Feedback
CY22050,
CY220501
CY22050 Frequency Calculation
The CY22050 is an extremely flexible clock generator with up to
six individual outputs, generated from an integrated PLL.
There are four variables used to determine the final output
frequency. They are: the input REF, the P and Q dividers, and
the post divider. The three basic formulas for determining the
final output frequency of a CY22150-based design are:
■
■
■
and can be independent of each other. The post divider options
can be applied to the calculated PLL frequency or to the REF
directly.
In addition to the six post divider options, the seventh option
bypasses the PLL and passes the REF directly to the crosspoint
switch matrix.
CLK = ((REF * P)/Q)/Post Divider
CLK = REF/Post Divider
CLK = REF
Clock Output Settings: Crosspoint Switch
Matrix
Each of the six clock outputs can come from any of seven unique
frequency sources. The crosspoint switch matrix defines which
source is attached to each individual clock output. Although it
may seem that there are an unlimited number of divider options,
there are several rules that must be taken into account when
selecting divider options.
The basic PLL block diagram is shown in
Figure 2.
Each of the
six clock outputs has a total of seven output options available to
it. There are six post divider options: /2 (two of these), /3, /4,
/DIV1N, and DIV2N. DIV1N and DIV2N are separately calculated
Figure 2. Basic PLL Block Diagram
Divider Bank 1
/DIV1N
LCLK1
LCLK2
LCLK3
Crosspoint
Switch
Matrix
REF
Q
PFD
P
VCO
/2
/
3
Divider Bank 2
LCLK4
CLK5
CLK6
/
4
/
2
/DIV2N
Table 3. Clock Output Definition
Clock Output Divider
None
/DIV1N
/2
/3
/DIV2N
/2
/4
Definition and Notes
Clock output source is the reference input frequency
Clock output uses a generated /DIV1N option from Divider Bank 1. Allowable values for DIV1N are 4 to 127.
If Divider Bank 1 is not being used, set DIV1N to 8.
Clock output uses a fixed /2 option from Divider Bank 1. If this option is used, DIV1N must be divisible by 4.
Clock output uses a fixed /3 option from Divider Bank 1. If this option is used, set DIV1N to 6.
Clock output uses a generated /DIV2N option from Divider Bank 2. Allowable values for DIV2N are 4 to 127.
If Divider Bank 2 is not being used, set DIV2N to 8.
Clock output uses a fixed /2 option from Divider Bank 2. If this option is used, DIV2N must be divisible by 4.
Clock output 2 uses a fixed /4 option from Divider Bank 2. If this option is used, DIV2N must be divisible by 8.
Document #: 38-07006 Rev. *G
Page 4 of 10
[+] Feedback
MicroPython开源版块
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
