CY22050,
CY220501
One-PLL General-Purpose
Flash-Programmable Clock Generator
Features
■
■
■
■
■
■
■
■
■
— 80 kHz–200 MHz (3.3 V)
— 80 KHz–166.6 MHz (2.5 V)
❐
Industrial temperature
— 80 kHz–166.6 MHz (3.3 V)
— 80 KHz–150 MHz (2.5 V)
Integrated phase-locked loop (PLL)
Commercial and Industrial operation
Flash-programmable
Field-programmable
Low-skew, low-jitter, high-accuracy outputs
3.3 V operation with 2.5 V output option
16-pin TSSOP package (CY22050)
16-pin TSSOP package with NiPdAu lead finish (CY220501)
Input freqency range:
— 8 MHz–30 MHz (external crystal)
— 1 MHz–133 MHz (driven clock)
Functional Description
The CY22050 is programmable clock generator for use in
networking,
telecommunication,
datacom,
and
other
general-purpose applications. The CY22050 offers up to six
configurable outputs in a 16-pin TSSOP, running off a 3.3 V
power supply. The on-chip reference oscillator is designed to run
off an 8–30-MHz crystal, or a 1–133-MHz external clock signal.
The CY22050 has a single PLL driving 6 programmable output
clocks. The output clocks are derived from the PLL or the
reference frequency (REF). Output post dividers are available for
either. Four of the outputs can be set as 3.3 V or 2.5 V, for use
in a wide variety of portable and low-power applications.
The CY220501 is the CY22050 with NiPdAu lead finish.
■
Output freqency range:
❐
Commercial temperature
Logic Block Diagram
LCLK1
Divider
Bank 1
Output
Select
Matrix
VCO
P
PLL
Divider
Bank 2
CLK5
CLK6
LCLK2
LCLK3
LCLK4
XIN
XOUT
OSC.
Q
OE
VDD
AVDD AVSS
VSS
VDDL
VSSL
PWRDWN
Cypress Semiconductor Corporation
Document #: 38-07006 Rev. *J
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised March 30, 2011
[+] Feedback
CY22050,
CY220501
Pin Configuration
Figure 1. 16-Pin TSSOP
XIN
VDD
AVDD
PWRDWN
AVSS
VSSL
LCLK1
LCLK2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
XOUT
CLK6
CLK5
VSS
LCLK4
VDDL
OE
LCLK3
Table 1. Pin Definitions
Name
XIN
Pin Number
1
Description
Reference Input. Driven by a crystal (8 MHz–30 MHz) or external clock (1 MHz–133 MHz).
Programmable input load capacitors allow for maximum flexibility in selecting a crystal, based on
manufacturer, process, performance, or quality.
3.3 V voltage supply
3.3 V analog voltage supply
Power Down. When pin 4 is driven LOW, the CY22050 goes into shut down mode.
Analog ground
LCLK ground
Configurable clock output 1 at V
DDL
level (3.3 V or 2.5 V)
Configurable clock output 2 at V
DDL
level (3.3 V or 2.5 V)
Configurable clock output 3 at V
DDL
level (3.3 V or 2.5 V)
Output Enable. When pin 10 is driven LOW, all outputs are three-stated.
LCLK voltage supply (2.5 V or 3.3 V)
Configurable clock output 4 at V
DDL
level (3.3 V or 2.5 V)
Ground
Configurable clock output 5 (3.3 V)
Configurable clock output 6 (3.3 V)
Reference output
VDD
AVDD
PWRDWN
[1]
AVSS
VSSL
LCLK1
LCLK2
LCLK3
OE
[1]
VDDL
LCLK4
VSS
CLK5
CLK6
XOUT
[2]
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Notes
1. The CY22050 has no internal pull up or pull down resistors. PWRDWN and OE pins need to be driven as appropriate or tied to power or ground.
2. Float XOUT if XIN is driven by an external clock source.
Document #: 38-07006 Rev. *J
Page 2 of 11
[+] Feedback
CY22050,
CY220501
Field Programming the CY22050F
The CY22050 is programmed at the package level, that is, in a
programmer socket, prior to installation on a PCB. The CY22050
is flash-technology based, so the parts can be reprogrammed up
to 100 times. This allows for fast and easy design changes and
product updates, and eliminates any issues with old and
out-of-date inventory.
Samples and small prototype quantities can be programmed on
the CY3672 programmer. Cypress’s value-added distribution
partners and third-party programming systems from BP Micro-
systems, HiLo Systems, and others are available for
large-production quantities.
Applications
Controlling Jitter
Jitter is defined in many ways, including: phase noise, long-term
jitter, cycle-to-cycle jitter, period jitter, absolute jitter, and deter-
ministic jitter. These jitter terms are usually given in terms of rms,
peak-to-peak, or in the case of phase noise dBC/Hz with respect
to the fundamental frequency. Actual jitter is dependent on XIN
jitter and edge rate, number of active outputs, output
frequencies, V
DDL
(2.5 V or 3.3 V), temperature, and output load.
Power supply noise and clock output loading are two major
system sources of clock jitter. Power supply noise can be
mitigated by proper power supply decoupling (0.1-F ceramic
cap) of the clock and ensuring a low-impedance ground to the
chip. Reducing capacitive clock output loading to a minimum
lowers current spikes on the clock edges and thus reduces jitter.
Reducing the total number of active outputs also reduce jitter in
a linear fashion. However, it is better to use two outputs to drive
two loads than one output to drive two loads.
The rate and magnitude that the PLL corrects the VCO frequency
is directly related to jitter performance. If the rate is too slow, then
long term jitter and phase noise is poor. Therefore, to improve
long-term jitter and phase noise, reducing Q to a minimum is
advisable. This technique increases the speed of the phase
frequency detector, which in turn drives the input voltage of the
VCO. In a similar manner, increasing P until the VCO is near its
maximum rated speed also decreases long term jitter and phase
noise. For example: input reference of 12 MHz; desired output
frequency of 33.3 MHz. One might arrive at the following
solution: Set Q = 3, P = 25, Post Div = 3. However, the best jitter
results are Q = 2, P = 50, Post Div = 9.
For additional information, refer to the application note, “Jitter in
PLL-based Systems: Causes, Effects, and Solutions,” available
at
http://www.cypress.com
(click on “Application Notes”), or
contact your local Cypress Field Applications Engineer.
CyberClocks Software
CyberClocks is an easy-to-use software application that allows
the user to custom-configure the CY22050. Within CyberClocks,
select the CyClocksRT
tool. Users can specify the REF, PLL
frequency, output frequencies and/or post-dividers, and different
functional options. CyClocksRT outputs an industry-standard
JEDEC file used for programming the CY22050.
CyClocksRT can be downloaded free of charge from the
Cypress website at
http://www.cypress.com.
Install and run it on
any PC running the Windows operating system.
CY3672 Development Kit
The Cypress CY3672 Development Kit comes complete with
everything needed to design with the CY22050 and program
samples and small prototype quantities. The kit comes with the
latest version of CyClocksRT and a small portable programmer
that connects to a PC for on-the-fly programming of custom
frequencies.
The JEDEC file output of CyClocksRT can be downloaded to the
portable programmer for small-volume programming, or for use
with a production programming system for larger volumes.
Document #: 38-07006 Rev. *J
Page 3 of 11
[+] Feedback
CY22050,
CY220501
CY22050 Frequency Calculation
The CY22050 is an extremely flexible clock generator with up to
six individual outputs, generated from an integrated PLL.
There are four variables used to determine the final output
frequency. They are: the input REF, the P and Q dividers, and
the post divider. The three basic formulas for determining the
final output frequency of a CY22150-based design are:
■
■
■
and can be independent of each other. The post divider options
can be applied to the calculated PLL frequency or to the REF
directly.
In addition to the six post divider options, the seventh option
bypasses the PLL and passes the REF directly to the crosspoint
switch matrix.
CLK = ((REF * P)/Q)/Post Divider
CLK = REF/Post Divider
CLK = REF
Clock Output Settings: Crosspoint Switch
Matrix
Each of the six clock outputs can come from any of seven unique
frequency sources. The crosspoint switch matrix defines which
source is attached to each individual clock output. Although it
may seem that there are an unlimited number of divider options,
there are several rules that must be taken into account when
selecting divider options.
The basic PLL block diagram is shown in
Figure 2.
Each of the
six clock outputs has a total of seven output options available to
it. There are six post divider options: /2 (two of these), /3, /4,
/DIV1N, and DIV2N. DIV1N and DIV2N are separately calculated
Figure 2. Basic PLL Block Diagram
Divider Bank 1
/DIV1N
LCLK1
LCLK2
LCLK3
Crosspoint
Switch
Matrix
REF
Q
PFD
P
VCO
/2
/
3
Divider Bank 2
LCLK4
CLK5
CLK6
/
4
/
2
/DIV2N
Table 2. Clock Output Definition
Clock Output Divider
None
/DIV1N
/2
/3
/DIV2N
/2
/4
Definition and Notes
Clock output source is the reference input frequency
Clock output uses a generated /DIV1N option from Divider Bank 1. Allowable values for DIV1N are 4 to 127.
If Divider Bank 1 is not being used, set DIV1N to 8.
Clock output uses a fixed /2 option from Divider Bank 1. If this option is used, DIV1N must be divisible by 4.
Clock output uses a fixed /3 option from Divider Bank 1. If this option is used, set DIV1N to 6.
Clock output uses a generated /DIV2N option from Divider Bank 2. Allowable values for DIV2N are 4 to 127.
If Divider Bank 2 is not being used, set DIV2N to 8.
Clock output uses a fixed /2 option from Divider Bank 2. If this option is used, DIV2N must be divisible by 4.
Clock output 2 uses a fixed /4 option from Divider Bank 2. If this option is used, DIV2N must be divisible by 8.
Document #: 38-07006 Rev. *J
Page 4 of 11
[+] Feedback
CY22050,
CY220501
Reference Crystal Input
The input crystal oscillator of the CY22050 is an important
feature because of the flexibility it allows the user in selecting a
crystal as a reference clock source. The oscillator inverter has
programmable gain, allowing for maximum compatibility with a
reference crystal, based on manufacturer, process,
performance, and quality.
The value of the input load capacitors is determined by eight bits
in a programmable register. Total load capacitance is determined
by the formula:
CapLoad = (C
L
– C
BRD
– C
CHIP
)/0.09375 pF
In CyClocksRT, enter the crystal capacitance (C
L
). The value of
CapLoad is determined automatically and programmed into the
CY22050.
If you require greater control over the CapLoad value, consider
using the CY22150 for serial configuration and control of the
input load capacitors. For an external clock source, the default is
0.
Input load capacitors are placed on the CY22050 die to reduce
external component cost. These capacitors are true
parallel-plate capacitors, designed to reduce the frequency shift
that occurs when non-linear load capacitance is affected by load,
bias, supply, and temperature changes.
Crystal Drive Level and Power
Crystals are specified to accept a maximum drive level.
Generally, larger crystals can accept more power. The drive level
specification in the table below is a general upper bound for the
power driven by the oscillator circuit in the CY22050.
For a given voltage swing, power dissipation in the crystal is
proportional to ESR and proportional to the square of the crystal
frequency. (Note that actual ESR is sometimes much less than
the value specified by the crystal manufacturer.) Power is also
almost proportional to the square of C
L
.
Power can be reduced to less than the DL specification in the
table below by selecting a reduced frequency crystal with low C
L
and low R
1
(ESR).
Absolute Maximum Conditions
Parameter
V
DD
V
DDL
T
S
T
J
Supply Voltage
I/O Supply Voltage
Storage Temperature
[3]
Junction Temperature
Package Power Dissipation—Commercial Temp
Package Power Dissipation—Industrial Temp
Digital Inputs
Digital Outputs referred to V
DD
Digital Outputs referred to V
DDL
ESD
Static Discharge Voltage per MIL-STD-833, Method 3015
AV
SS
– 0.3
V
SS
– 0.3
V
SS
– 0.3
Description
Min
–0.5
–0.5
–65
Max
7.0
7.0
125
125
450
380
AV
DD
+ 0.3
V
DD
+ 0.3
V
DDL
+0.3
2000
Unit
V
V
°C
°C
mW
mW
V
V
V
V
Recommended Operating Conditions
Parameter
V
DD
VDDL
HI
VDDL
LO
T
AC
T
AI
C
LOAD
C
LOAD
f
REFD
f
REFC
t
PU
Operating Voltage
Operating Voltage
Operating Voltage
Ambient Commercial Temp
Ambient Industrial Temp
Max. Load Capacitance V
DD
/V
DDL
= 3.3 V
Max. Load Capacitance V
DDL
= 2.5 V
Driven REF
Crystal REF
Power up time for all V
DD
s to reach minimum specified
voltage (power ramps must be monotonic)
1
8
0.05
Description
Min
3.135
3.135
2.375
0
–40
Typ.
3.3
3.3
2.5
Max
3.465
3.465
2.625
70
85
15
15
133
30
500
Unit
V
V
V
°C
°C
pF
pF
MHz
MHz
ms
Note
3. Rated for 10 years
Document #: 38-07006 Rev. *J
Page 5 of 11
[+] Feedback
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
