CY25200
Programmable Spread Spectrum
Clock Generator for EMI Reduction
Features
• Wide operating output (SSCLK) frequency range
— 3–200 MHz
• Programmable spread spectrum with nominal 31.5-kHz
modulation frequency.
• Center spread: ±0.25% to ±2.5%
• Down spread: –0.5% to –5.0%
• Input frequency range:
— External crystal: 8–30 MHz fundamental crystals
— External reference: 8–166 MHz Clock
• Integrated phase-locked loop (PLL)
• Programmable crystal load capacitor tuning array
• Low cycle-to-cycle Jitter
• 3.3V operation with 2.5V output clock drive option
• Spread spectrum On/Off function
• Power-down or Output Enable function
• Output frequency select option
Benefits
• Suitable for most PC peripherals, networking, and consum-
er applications.
• Provides wide range of spread percentages for maximum
EMI reduction, to meet regulatory agency Electro Magnetic
Compliance (EMC) requirements. Reduces development
and manufacturing costs and time-to-market.
• Eliminates the need for expensive and difficult to use higher
order crystals.
• Internal PLL generates up to 200 MHz outputs, and can
generate custom frequencies from an external crystal or a
driven source.
• Enables fine-tuning of output clock frequency by adjusting
C
Load
of the crystal. Eliminates the need for external C
Load
capacitors.
• Application compatibility in standard and low-power sys-
tems.
• Provides ability to enable or disable spread spectrum with
an external pin.
• Enables low-power state or output clocks to High-Z state.
Logic Block Diagram
7
Divider
Bank 1
Output
Select
Matrix
VCO
P
Divider
Bank 2
SSCLK1
8
SSCLK2
9
SSCLK3
XIN/CLKIN 1
XOUT
16
C
XOUT
OSC.
C
XIN
Q
Φ
12
SSCLK4
PLL
14
SSCLK5/REFOUT/CP2
15
SSCLK6/REFOUT/CP3
2
3
AVDD
5
AVSS
13
VSS
11
VDDL
6
VSSL
4
CP0
10
CP1
Pin Configuration
VDD
XIN
VDD
AVDD
CP0
AVSS
VSSL
SSCLK1
SSCLK2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
XOUT
SSCLK6
/REFOUT/CP3
SSCLK5
/REFOUT/CP2
VSS
SSCLK4
VDDL
CP1
SSCLK3
Cypress Semiconductor Corporation
Document #: 38-07633 Rev. *A
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Revised April 22, 2004
CY25200
General Description
The CY25200 is a Spread Spectrum Clock Generator (SSCG)
IC used for the purpose of reducing Electro Magnetic Inter-
ference (EMI) found in today’s high-speed digital electronic
systems.
The device uses a Cypress proprietary Phase-Locked Loop
(PLL) and Spread Spectrum Clock (SSC) technology to
synthesize and modulate the frequency of the input clock. By
frequency modulating the clock, the measured EMI at the
fundamental and harmonic frequencies are greatly reduced.
This reduction in radiated energy can significantly reduce the
cost of complying with regulatory agency requirements (EMC)
and improve time to market without degrading system perfor-
mance.
The CY25200 uses a factory-programmable configuration
memory array to synthesize output frequency, spread %,
crystal load capacitor, clock control pins, PD# and OE options.
The spread % is factory programmed to either center spread
or down spread with various spread percentages. The range
for center spread is from ±0.25% to ±2.50%. The range for
down spread is from –0.5% to –5.0%. Contact the factory for
smaller or larger spread % amounts if required.
The input to the CY25200 can be either a crystal or a clock
signal. The input frequency range for crystals is 8–30 MHz,
and for clock signals is 8–166 MHz.
The CY25200 has six clock outputs, SSCLK1 to SSCLK6. The
frequency modulated SSCLK outputs can be programmed
from 3–200 MHz.
The CY25200 products are available in a 16-pin TSSOP
package with a commercial operating temperature range of 0
to 70°C.
CY25200 Pin Summary
Name
XIN
XOUT
VDD
AVDD
VSS
AVSS
VDDL
VSSL
SSCLK1
SSCLK2
SSCLK3
SSCLK4
SSCLK5/REFOUT/CP2
SSCLK6/REFOUT/CP3
CP0
[1]
CP1
[1]
Pin Number
1
16
2
3
13
5
11
6
7
8
9
12
14
15
4
10
Description
Crystal Input or Reference Clock Input.
Crystal Output.
Leave this pin floating if external clock is used.
3.3V Power supply for digital logic and SSCLK5/6 clock drives.
3.3V analog–PLL power supply
Ground
Analog ground
2.5V or 3.3V power supply for SSCLK1/2/3/4 clock drives
VDDL power supply ground
Programmable Spread Spectrum Clock Output at VDDL Level (2.5V or 3.3V)
Programmable Spread Spectrum Clock Output at VDDL Level (2.5V or 3.3V)
Programmable Spread Spectrum Clock Output at VDDL Level (2.5V or 3.3V)
Programmable Spread Spectrum Clock Output at VDDL Level (2.5V or 3.3V)
Programmable Spread Spectrum Clock or Buffered Reference Output at VDD
Level (3.3V) or Control pin, CP2
Programmable Spread Spectrum Clock or Buffered Reference Output at VDD
Level (3.3V) or Control pin, CP3
Control Pin 0
Control Pin 1
Note:
1. Pins can be programmed to be any of the following control signals: OE: Output Enable, OE = 1 all the SSCLK outputs are enabled, PD#: Powerdown, PD#
= 0, all the SSCLK outputs are three-stated and the part enters a low-power state, SSON: Spread Spectrum Control (SSON = 0, No Spread and SSON = 1,
Spread Signal), CLKSEL: SSCLK Output Frequency Select. Please see page 3 for control pins programming option.
Document #: 38-07633 Rev. *A
Page 2 of 11
CY25200
Table 1. Fixed Function Pins
Pin
Function
Pin Name
Pin#
Units
Program Value
CLKSEL = 0
Program Value
CLKSEL = 1
Output Clock Functions and Frequency
SSCLK1
7
MHz
ENTER
DATA
ENTER
DATA
SSCLK2
8
MHz
ENTER
DATA
ENTER
DATA
SSCLK3
9
MHz
ENTER
DATA
ENTER
DATA
SSCLK4
12
MHz
ENTER
DATA
ENTER
DATA
Input
Frequency
XIN and
XOUT
1 and 16
MHz
C
XIN
and
C
XOUT
XIN and
XOUT
1 and 16
pF
Spread
Percent
SSCLK[1:6]
Frequency
Modulation
SSCLK[1:6]
7,8,9,12,14,15 7,8,9,12,14,15
%
kHz
ENTER
DATA
ENTER
DATA
ENTER
DATA
31.5
Table 2. Multi-function Pins
Pin
Function
Pin Name
Pin#
Units
Program Value
CLKSEL = 0
Program Value
CLKSEL = 1
Output Clock /REFOUT /OE/SSON/CLKSEL
SSCLK5/REFOUT/CP2
14
MHz
ENTER DATA
ENTER DATA
SSCLK6/REFOUT/CP3
15
MHz
ENTER DATA
ENTER DATA
ENTER DATA
ENTER DATA
OE/PD#/SSON/CLKSEL
CP0
4
N/A
CP1
10
N/A
Programming Description
Customers planning to use the CY25200 need to provide the
programming information described as “ENTER DATA” in
Table 1 and Table 2,
then should contact local Cypress Sales.
Additional information on the CY25200 can be obtained from
the Cypress web site at www.cypress.com.
• Output Enable (OE), if OE = 1, all the SSCLK or REFOUT
outputs are enabled
• SSON, Spread spectrum control, 1 = spread on and 0 =
spread off
• CLKSEL, SSCLK output frequency select
• PD#, Active Low, PD# = 0, all the outputs are three-stated
and the part enters a low-power state
• The last control signal is the Power down (PD#) that can be
implemented only through programming CP0 or CP1 (CP2
and CP3 can not be programmed as PD#). Here is an ex-
ample with 3 control pins,
• CLKIN = 33MHz
• SSCLK1/2/3/4 = 100MHz with ±1% Spread
• SSCLK 5 = REFOUT(33MHz)
• CP0 (Pin 4) = PD#
• CP1 (Pin 10) = OE
• CP3 (pin 15) = SSON
The pinout for the above example is shown in
Figure 1.
NC
SSON
REFOUT(33.0MHz)
Product Functions
Control Pins (CP0, CP1, CP2 and CP3)
There are four control signals available through programming
of pins 4, 10, 14 and 15.
CP0 (pin 4) and CP1 (pin10) are specifically designed to
function
as
control
pins.
However
pins
14
(SSCLK5/REFOUT/CP2) and 15 (SSCLK6/REFOUT/CP3)
are multi-functional and can be programmed to be a control
signal or an output clock (SSCLK or REFOUT). All of the
control pins, CP0, CP1, CP2 and CP3 are programmable and
can be programmed to have only one of the following
functions:
33.0MHz
VDD
AVDD
PD#
AVSS
VSSL
100MHz
100MHz
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VSS
100MHz
VDDL
OE
100MHz
Figure 1.
Document #: 38-07633 Rev. *A
Page 3 of 11
CY25200
The CLKSEL control pin enables the user to change the output
frequency from one frequency (e.g., frequency A) to another
frequency (e.g., frequency B). These must be related
frequencies that can be derived off of a common VCO
frequency, e.g., 33.333 MHz and 66.666 MHz can both be
derived from a VCO = 400 MHz and dividing it down by 12 and
6 respectively.
Table 3
shows an example of how this can be
implemented. The VCO frequency range is 100–400MHz. The
CY25200 has two separate dividers, Divider 1 and Divider 2,
these two can be loaded to have any number between 2 and
130 providing two different but related frequencies as
explained above.
In the above example SSCLK5 (pin 14) and SSCLK6(pin 15)
are used as output clocks, however they could have been
used as control signals. See
Figure 2
for the pinout.
Input Frequency (XIN, pin 1 and XOUT
,
pin 16)
The input to the CY25200 can be a crystal or a clock. The input
frequency range for crystals is 8 to 30 MHz, and for clock sig-
nal is 8 to 166 MHz.
C
XIN
and C
XOUT
(pin 1 and pin 16)
The load capacitors at pin 1 (C
XIN
) and pin 16 (C
XOUT
) can be
programmed from 12 pF to 60 pF with 0.5-pF increments. The
programmed value of these on-chip crystal load capacitors are
the same (XIN = XOUT = 12 to 60 pF).
The required values of
C
XIN
and
C
XOUT
for matching crystal
load (CL) can be calculated using the following formula:
C
XIN
= C
XOUT
= 2C
L
– C
P
Where C
L
is the crystal load capacitor as specified by the crys-
tal manufacturer and C
P
is the parasitic PCB capacitance.
Table 3. Using Clock Select, CLKSEL Control Pin
Input Freq.
(MHz)
14.318
CLKSEL
(Pin 4)
CLKSEL = 0
CLKSEL = 1
SSCLK1
(Pin 7)
33.33
66.66
SSCLK2
(Pin 8)
33.33
66.66
SSCLK3
(Pin 9)
33.33
66.66
SSCLK4
(Pin 12)
33.33
66.66
REFOUT
(Pin 14)
14.318
14.318
REFOUT
(Pin 15)
14.318
14.318
For example, if a fundamental 16-MHz crystal with C
L
of 16 pF
is used and C
P
is 2 pF, C
XIN
and C
XOUT
can be calculated as:
C
XIN
= C
XOUT
= (2 x 16) – 2 = 30 pF.
If using a driven reference clock, set C
XIN
and C
XOUT
to the
minimum value 12 pF.
Output Frequency (SSCLK1 through SSCLK6 Outputs)
All of the SSCLK outputs are produced by synthesizing the
input reference frequency using a PLL and modulating the
VCO frequency. SSCLK[1:4] can be programmed to be only
output clocks (SSCLK). SSCLK5 and SSCLK6 can also be
programmed to function the same as SSCLK[1:4] or a buffered
copy of the input reference (REFOUT) or they can be
programmed to be a control pin as discussed in the control
pins section. To utilize the 2.5V output drive option on
SSCLK[1:4], VDDL must be connected to a 2.5V power supply
(SSCLK[1:4] outputs are powered by VDDL). When using the
2.5V output drive option, the maximum output frequency on
SSCLK[1:4] is 166MHz.
Spread Percentage (SSCLK1 through SSCLK6 Outputs)
The SSCLK frequency can be programmed at any percentage
value from ±0.25% to ±2.5% for Center Spread and from
–0.5% to –5.0% Down Spread.
Frequency Modulation
The frequency modulation is programmed at 31.5 kHz for all
SSCLK frequencies from 3 to 200 MHz. Contact the factory if
a higher modulation frequency is required.
14.318MHz
VDD
AVDD
CLKSEL
AVSS
VSSL
33.33/66.66MHz
33.33/66.66MHz
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
XOUT
REFOUT(14.318MHz)
REFOUT(14.318MHz)
VSS
33.33/66.66MHz
VDDL
SSON
33.33/66.66MHz
Figure 2.
Table 3
Configuration Pinout
Document #: 38-07633 Rev. *A
Page 4 of 11
CY25200
Switching Waveforms
Duty Cycle Timing (DC = t
1A
/t
1B
)
OUTPUT
t
1A
t
1B
Output Rise/Fall Time (SSCLK and REFCLK)
V
DD
0V
Tr
Tf
Output Rise time (Tr) = (0.6 x V
DD
)/SR1 (or SR3)
Output Fall time (Tf) = (0.6 x V
DD
)/SR2 (or SR4)
Refer to AC Electrical Characteristics table for SR (Slew Rate) values.
OUTPUT
Power-down Timing and Power-up Timing
POWER-
DOWN
V
DD
0V
V
IL
V
IH
t
PU
(Asynchronous
SSCLK
High Impedance
t
STP
)
Output Enable/Disable Timing
OUTPUT
ENABLE
V
DD
0V
V
IL
V
IH
T
OE2
(Asynchronous
)
SSCLK
T
OE1
High Impedance
Document #: 38-07633 Rev. *A
Page 5 of 11
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