19-0729; Rev 2; 12/09
PECI-to-I
2
C Translator
General Description
The MAX6621 PECI-to-I
2
C translator provides an effi-
cient, low-cost solution for PECI-to-SMBus
TM
/I
2
C proto-
col conversion. The PECI-compliant host reads
temperature data directly from up to four PECI-enabled
CPUs. Interrupts are generated when the measured
temperature exceeds the high-temperature limit and
causes
ALERT
to assert. The
RESET
input allows the
host to reset the I
2
C bus in the event of a communica-
tion error.
The I
2
C interface provides an independent serial com-
munication channel to communicate synchronously with
peripheral devices in a multiple master or multiple slave
system. This interface allows a maximum serial-data
rate of 400kbps.
The MAX6621 is designed to operate from a +3.0V to
+3.6V supply voltage and ambient temperature range
of -20°C to +120°C.
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
Features
400kbps I
2
C-Compatible, 2-Wire Serial Interface
+3V to +3.6V Supply Voltage
PECI-Compliant Port
PECI-to-I
2
C Translation
ALERT
Output
RESET
Input (May Be Disabled as a Factory
Option)
Programmable Temperature Offsets
-20°C to +120°C Operating Temperature Range
V
REF
Input Refers Logic Levels to the PECI
Supply Voltage
Automatic I
2
C Bus Lockup Timeout Reset
Lead-Free, 10-Pin
µMAX
®
Package
MAX6621
Applications
Servers
Workstations
Desktop Computers
PART
MAX6621AUB+
MAX6621AUB+T
Ordering Information
TEMP RANGE
-20°C to +120°C
-20°C to +120°C
PIN-PACKAGE
10 μMAX
10 μMAX
T = Tape and reel.
+Denotes
a lead(Pb)-free/RoHS-compliant package.
SMBus is a trademark of Intel Corp.
μMAX is a registered trademark of Maxim Integrated Products, Inc.
Pin Configuration appears at end of data sheet.
Typical Application Circuit
+3.3V
V
CPU
V
TT
V
CC
SDA
I
2
C
MASTER
SCL
SDA
SCL
RESET
ALERT
AD0
GND
V
REF
CPU
INTERNAL
TEMP
SENSOR
MAX6621
PECI
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
PECI-to-I
2
C Translator
MAX6621
ABSOLUTE MAXIMUM RATINGS
(All voltages with respect to GND.)
V
CC
..........................................................................-0.3V to +4V
AD0,
RESET, ALERT...................................-0.3V
to (V
CC
+ 0.3V)
SCL, SDA .................................................................-0.3V to +6V
V
REF
.........................................................................-0.3V to +4V
PECI .........................................................-0.3V to (V
REF
+ 0.3V)
DC Current through SDA ...................................................10mA
Continuous Power Dissipation (T
A
= +70°C)
10-Pin μMAX (derate 5.6mW/°C over T
A
= +70°C)......444mW
Operating Temperature Range .........................-20°C to +120°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Typical
Application Circuit,
V
CC
= +3V to +3.6V, V
REF
= +0.95V to +1.26V, T
A
= -20°C to +120°C, unless otherwise noted. Typical
values are at V
CC
= +3.3V, V
REF
= +1.0V, T
A
= +25°C.) (Note 1)
PARAMETER
SUPPLY
Operating Supply Voltage
Operating Supply Current
Power-On-Reset Voltage
INPUT SCL, INPUT/OUTPUT SDA
Low-Level Input Voltage
High-Level Input Voltage
Low-Level Output Voltage
Leakage Current
Input Capacitance
ALERT
Low-Level Output Voltage
ADDRESS INPUT AD0/RST
Low-Level Input Voltage
High-Level Input Voltage
Leakage Current
Input Capacitance
PECI
Supply Voltage to PECI Cell
Input Voltage Range
Low-Level Input Voltage
Threshold
High-Level Input Voltage
Threshold
V
REF
V
IN
V
IL
V
IH
0.95
-0.3
0.275
x V
REF
0.550
x V
REF
1.26
V
REF
+ 0.3
0.500
x V
REF
0.725
x V
REF
V
V
V
V
V
IL
V
IH
I
L
C
I
0.7
x V
CC
-2
10
0.3
x V
CC
V
CC
+ 0.3
+2
V
V
μA
pF
V
OL
I
OL
= 6mA
0.4
V
V
IL
V
IH
V
OL
I
L
C
I
I
OL
= 6mA
-1
10
0.7
x V
CC
0.3
x V
CC
5.5
0.4
+1
V
V
V
μA
pF
V
CC
I
CC
V
POR
SCL = 400kHz
2.60
3.0
4
3.6
7
2.95
V
mA
V
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
2
_______________________________________________________________________________________
PECI-to-I
2
C Translator
ELECTRICAL CHARACTERISTICS (continued)
(Typical
Application Circuit,
V
CC
= +3V to +3.6V, V
REF
= +0.95V to +1.26V, T
A
= -20°C to +120°C, unless otherwise noted. Typical
values are at V
CC
= +3.3V, V
REF
= +1.0V, T
A
= +25°C.) (Note 1)
PARAMETER
Hysteresis
Low-Level Sinking Current
High-Level Sourcing Current
Input Capacitance
Signal-Noise Immunity Above
300MHz
SYMBOL
V
H
I
IL
I
IH
C
I
V
N
(Note 2)
(Note 2)
0.1
x V
REF
CONDITIONS
MIN
0.1
x V
REF
0.5
-6
10
1.0
TYP
MAX
UNITS
V
mA
mA
pF
V
P-P
MAX6621
TIMING CHARACTERISTICS
(Typical
Application Circuit,
V
CC
= +3V to +3.6V, V
REF
= +0.95V to +1.26V, T
A
= -20°C to +120°C, unless otherwise noted. Typical
values are at V
CC
= +3.3V, V
REF
= +1.0V, T
A
= +25°C.) (Note 2)
PARAMETER
RESET
Pulse Width
I
2
C INTERFACE
Serial-Clock Frequency
Bus Free Time Between a
STOP and a START Condition
Hold Time, (Repeated) START
Condition
Repeated START Condition
Setup Time
STOP Condition Setup Time
Data Hold Time
Data Setup Time
SCL Clock-Low Period
SCL Clock-High Period
Rise Time of Both SDA and
SCL Signals, Receiving
Fall Time of Both SDA and
SCL Signals, Receiving
Fall Time of SDA Transmitting
Pulse Width of Spike
Suppressed
Capacitive Load for Each
Bus Line
PECI INTERFACE
Bit Time (Note 7)
t
BIT
Overall time evident on PECI
Driven by MAX6621
0.495
0.495
500
250
μs
f
SCL
t
BUF
t
HD, STA
t
SU, STA
t
SU, STO
t
HD, DAT
t
SU, DAT
t
LOW
t
HIGH
t
R
t
F
t
F.TX
t
SP
C
b
(Notes 4, 5)
(Notes 4, 5)
(Notes 4, 5)
(Note 6)
(Note 4)
50
(Note 3)
120
1.3
0.6
20
+ 0.1C
b
20
+ 0.1C
b
20
+ 0.1C
b
160
400
300
300
250
1.3
0.6
0.6
0.6
0.9
400
kHz
μs
μs
μs
μs
μs
ns
μs
μs
ns
ns
ns
ns
pF
SYMBOL
RST
CONDITIONS
MIN
100
TYP
MAX
UNITS
ns
_______________________________________________________________________________________
3
PECI-to-I
2
C Translator
MAX6621
TIMING CHARACTERISTICS (continued)
(Typical
Application Circuit,
V
CC
= +3V to +3.6V, V
REF
= +0.95V to +1.26V, T
A
= -20°C to +120°C, unless otherwise noted. Typical
values are at V
CC
= +3.3V, V
REF
= +1.0V, T
A
= +25°C.) (Note 2)
PARAMETER
Bit Time Jitter
SYMBOL
t
BIT, jitter
CONDITIONS
Between adjacent bits in an PECI message
header or data bytes after timing has been
negotiated
Across a PECI address or PECI message
bits as driven by MAX6621
(Note 8)
0.6
0.2
0
Measured from V
OL
to V
P
MAX,
V
REF(nom)
-5% (Note 9)
Measured from V
OH
to V
N
MAX,
V
REF(nom)
+5% (Note 9)
Time for client to maintain a low idle drive
after MAX6621 begins a message (Note 10)
A constant low level driven by MAX6621
(Notes 8, 11)
From the end of a ResetDevice command
to the next message to which the reset
client must be able to respond
If the prior t
BIT
is not known by MAX6621,
the maximum t
BIT
must be assumed and
t
SETUP
= 1ms in this case (Note 12)
2
MIN
TYP
1
MAX
UNITS
%
Change in Bit Time
High-Level Time for Logic-High
High-Level Time for Logic-Low
Client Asserts PECI High
During Logic-High
Rise Time
Fall Time
Hold Time
Stop Time
Maximum Dwell Time of the
PECI Client
t
BIT, drift
t
H1
t
H0
t
SU
t
R
t
F
t
HOLD
t
STOP
2
0.75
0.3
0.8
0.4
0.2
30 +
5/Node
30/Node
0.5
%
x t
BIT
x t
BIT
x t
BIT-M
ns
ns
x t
BIT-1
x t
BIT-M
t
RESET
0.4
ms
Minimum PECI Low Time
Preceding a Message
t
SETUP
2
x t
BIT-X
Note 1:
All parameters are tested at T
A
= +25°C. Specifications over temperature are guaranteed by design.
Note 2:
Guaranteed by design; not production tested.
Note 3:
A master device must provide a hold time of at least 300ns for the SDA signal (referred to V
IL
of the SCL signal) to bridge
the undefined region of SCL’s falling edge.
Note 4:
C
b
= total capacitance of one bus line in pF. t
R
and t
F
measured between 0.3 x V
CC
and 0.7 x V
CC
.
Note 5:
I
SINK
≤
6mA. C
b
= total capacitance of one bus line in pF. t
R
and t
F
measured between 0.3 x V
CC
and 0.7 x V
CC
.
Note 6:
Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
Note 7:
The MAX6621 must drive a more restrictive time to allow for quantized sampling errors by a client yet still attain the mini-
mum time less than 500μs. t
BIT
limits apply equally to t
BIT-A
and t
BIT-M
.
Note 8:
The minimum and maximum bit times are relative to t
BIT
defined in the timing negotiation pulse.
Note 9:
Extended trace lengths can appear as additional nodes.
Note 10:
The client may deassert its low idle drive prior to the falling edge of the first bit of the message by using the rising edge to
detect a message start. However, the time delay must be sufficient to qualify the rising edge as a true message rather than
a noise spike.
Note 11:
The message stop is defined by two consecutive periods when the bus has no rising edge. Tolerance around this time is
based on the t
BIT-M
error budget.
Note 12:
t
SETUP
is not additive with t
STOP
. Rather, these times may overlap.
4
_______________________________________________________________________________________
PECI-to-I
2
C Translator
Pin Description
PIN
1
2
3
4
5
6
7
8
9
10
NAME
PECI
AGND
AD0
SDA
SCL
V
CC
GND
RESET
ALERT
V
REF
Analog Ground
I
2
C Bus Device Address Selection Input
I
2
C Bus Data Input/Output
I
2
C Bus Clock Input/Output
Power Supply. Bypass to GND with a 0.1μF capacitor.
Power-Supply Ground
I
2
C Reset Input. Pull
RESET
low to reset I
2
C interface and default all registers to startup values.
Drive high for normal operation.
ALERT
Interrupt Open-Drain Output. Asserts low when any temperature exceeds the
programmed limit.
PECI Input Supply Voltage. Bypass V
REF
to AGND with a 0.1μF capacitor.
FUNCTION
Platform Environment Control Interface (PECI) Serial-Bus Input/Output
MAX6621
Block Diagram
MAX6621
SDA
I
2
C
PORT
SCL
RESET
ALERT
PECI
TRANSLATION
ENGINE
AD0
PECI
PECI
PORT
V
REF
_______________________________________________________________________________________
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
