COM20020I 3.3V
5Mbps ARCNET (ANSI
878.1) Controller with
2K x 8 On-Chip RAM
Datasheet
Product Features
New Features:
-
-
Data Rates up to 5 Mbps
Programmable Reconfiguration Times
Eight, 256 Byte Pages Allow Four Pages TX and
RX Plus Scratch-Pad Memory
Next ID Readable
Internal Clock Scaler and Clock Multiplier for
Adjusting Network Speed
o
o
Operating Temperature Range of -40 C to +85 C
28 Pin PLCC and 48 Pin TQFP Packages;
Lead-free RoHS Compliant Packages also
available
Ideal for Industrial/Factory/Building Automation
and Transportation Applications
Deterministic, (ANSI 878.1), Token Passing
ARCNET Protocol
Minimal Microcontroller and Media Interface
Logic Required
Flexible Interface For Use With All
Microcontrollers or Microprocessors
Automatically Detects Type of Microcontroller
Interface
2Kx8 On-Chip Dual Port RAM
Command Chaining for Packet Queuing
Sequential Access to Internal RAM
Software Programmable Node ID
Self-Reconfiguration Protocol
Supports up to 255 Nodes
Supports Various Network Topologies (Star, Tree,
Bus...)
CMOS, Single +3.3V Supply
Duplicate Node ID Detection
Powerful Diagnostics
Receive All Packets Mode
Flexible Media Interface:
-
-
Traditional Hybrid Interface For Long
Distances up to Four Miles at 2.5Mbps
RS485 Differential Driver Interface For Low
Cost, Low Power, High Reliability
SMSC COM20020I 3.3V
1
Revision 12-06-06
DATASHEET
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
ORDERING INFORMATION
Order Numbers:
COM20020I3VLJP for 28 pin PLCC package
COM20020I3V-DZD for 28 pin PLCC package lead-free RoHS compliant package
COM20020I3V-HD for 48 pin TQFP package
COM20020I3V-HT for 48 pin TQFP lead-free RoHS compliant package
80 Arkay Drive
Hauppauge, NY 11788
(631) 435-6000
FAX (631) 273-3123
Copyright © 2006 SMSC or its subsidiaries. All rights reserved.
Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete
information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no
responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without
notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does
not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC
or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard
Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors
known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request.
SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause
or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further
testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale
Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems
Corporation (“SMSC”). Product names and company names are the trademarks of their respective holders.
SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES
OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND
ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY
DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR
REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC
OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO
HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
DAMAGES.
Revision 12-06-06
2
SMSC COM20020I 3.3V
DATASHEET
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
TABLE OF CONTENTS
2.0
3.0
4.0
5.0
5.1
5.2
5.3
5.4
5.5
5.6
6.0
6.1
6.2
7.0
7.1
7.2
7.3
7.4
7.5
7.6
8.0
8.1
8.2
9.0
10.0
11.0
12.0
12.1
GENERAL DESCRIPTION..............................................................................................................................5
PIN CONFIGURATIONS .................................................................................................................................6
DESCRIPTION OF PIN FUNCTIONS FOR TQFP ..........................................................................................8
PROTOCOL DESCRIPTION .........................................................................................................................11
N
ETWORK
P
ROTOCOL
..................................................................................................................................11
D
ATA
R
ATES
...............................................................................................................................................11
N
ETWORK
R
ECONFIGURATION
.......................................................................................................................12
B
ROADCAST
M
ESSAGES
...............................................................................................................................12
E
XTENDED
T
IMEOUT
F
UNCTION
.....................................................................................................................12
L
INE
P
ROTOCOL
..........................................................................................................................................13
SYSTEM DESCRIPTION...............................................................................................................................15
M
ICROCONTROLLER
I
NTERFACE
....................................................................................................................15
T
RANSMISSION
M
EDIA
I
NTERFACE
.................................................................................................................19
FUNCTIONAL DESCRIPTION ......................................................................................................................24
M
ICROSEQUENCER
......................................................................................................................................24
INTERNAL REGISTERS...........................................................................................................................25
I
NTERNAL
R
AM
............................................................................................................................................35
C
OMMAND
C
HAINING
....................................................................................................................................40
I
NITIALIZATION
S
EQUENCE
............................................................................................................................42
I
MPROVED
D
IAGNOSTICS
..............................................................................................................................42
OPERATIONAL DESCRIPTION ...................................................................................................................45
M
AXIMUM
G
UARANTEED
R
ATINGS
* ................................................................................................................45
D
C
E
LECTRICAL
C
HARACTERISTICS
...............................................................................................................45
TIMING DIAGRAMS......................................................................................................................................48
PACKAGE OUTLINES..................................................................................................................................60
APPENDIX A.................................................................................................................................................62
APPENDIX B.................................................................................................................................................65
S
OFTWARE
I
DENTIFICATION OF THE
COM20020I R
EV
B, R
EV
C
AND
R
EV
D .....................................................65
LIST OF FIGURES
Figure 1 - COM20020I OPERATION ...........................................................................................................................10
Figure 2 - MULTIPLEXED, 8051-LIKE BUS INTERFACE WITH RS-485 INTERFACE ...............................................16
Figure 3 - NON-MULTIPLEXED, 6801-LIKE BUS INTERFACE WITH RS-485 INTERFACE......................................17
Figure 4 - HIGH SPEED CPU BUS TIMING - INTEL CPU MODE...............................................................................18
Figure 5 - COM20020I NETWORK USING RS-485 DIFFERENTIAL TRANSCEIVERS................................................20
Figure 6 - DIPULSE WAVEFORM FOR DATA OF 1-1-0 .............................................................................................20
Figure 7 - INTERNAL BLOCK DIAGRAM ....................................................................................................................22
Figure 8 – SEQUENTIAL ACCESS OPERATION........................................................................................................35
Figure 9 – RAM BUFFER PACKET CONFIGURATION ..............................................................................................38
Figure 10 - COMMAND CHAINING STATUS REGISTER QUEUE ...............................................................................40
Figure 11 - MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; READ CYCLE ..................................................48
Figure 12 - MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; READ CYCLE ..................................................49
Figure 13 - MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; WRITE CYCLE.................................................50
SMSC COM20020I 3.3V
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Revision 12-06-06
DATASHEET
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
Figure 14 - MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; WRITE CYCLE.................................................51
Figure 15 - NON-MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; READ CYCLE .........................................52
Figure 16 - NON-MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; READ CYCLE .........................................53
Figure 17 - NON-MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; READ CYCLE .........................................54
Figure 18 - NON-MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; READ CYCLE .........................................55
Figure 19 - NON-MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; WRITE CYCLE .......................................56
Figure 20 - NON-MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; WRITE CYCLE .......................................57
Figure 21 – NORMAL MODE TRANSMIT OR RECEIVE TIMING ...............................................................................58
Figure 22 – BACKPLANE MODE TRANSMIT OR RECEIVE TIMING .........................................................................58
Figure 23 – TTL INPUT TIMING ON XTAL1 PIN .........................................................................................................59
Figure 24 – RESET AND INTERRUPT TIMING...........................................................................................................59
Figure 25 - 28 PIN PLCC PACKAGE DIMENSIONS ...................................................................................................60
Figure 26 - 48 PIN TQFP PACKAGE OUTLINE...........................................................................................................61
Figure 27 - EFFECT OF THE EF BIT ON THE TA/RI BIT ...........................................................................................63
LIST OF TABLES
Table 1 - Typical Media ................................................................................................................................................23
Table 2 - Read Register Summary...............................................................................................................................24
Table 3 - Write Register Summary ...............................................................................................................................25
Table 4 - Status Register ..............................................................................................................................................28
Table 5 - Diagnostic Status Register.............................................................................................................................29
Table 6 - Command Register........................................................................................................................................30
Table 7 - Address Pointer High Register .......................................................................................................................31
Table 8 - Address Pointer Low Register........................................................................................................................31
Table 9 - Sub Address Register ...................................................................................................................................31
Table 10 - Configuration Register ................................................................................................................................31
Table 11 - Setup 1 Register ..........................................................................................................................................33
Table 12 - Setup 2 Register ..........................................................................................................................................34
Revision 12-06-06
4
SMSC COM20020I 3.3V
DATASHEET
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
2.0 General Description
SMSC's COM20020I is a member of the family of Embedded ARCNET Controllers from Standard Microsystems
Corporation. The device is a general purpose communications controller for networking microcontrollers and intelligent
peripherals in industrial, automotive, and embedded control environments using an ARCNET protocol engine. The
flexible microcontroller and media interfaces, eight-page message support, and extended temperature range of the
COM20020I make it the only true network controller optimized for use in industrial, embedded, and automotive
applications. Using an ARCNET protocol engine is the ideal solution for embedded control applications because it
provides a deterministic token-passing protocol, a highly reliable and proven networking scheme, and a data rate of up
to 5 Mbps when using the COM20020I.
A token-passing protocol provides predictable response times because each network event occurs within a
predetermined time interval, based upon the number of nodes on the network. The deterministic nature of ARCNET is
essential in real time applications. The integration of the 2Kx8 RAM buffer on-chip, the Command Chaining feature, the
5 Mbps maximum data rate, and the internal diagnostics make the COM20020I the highest performance embedded
communications device available. With only one COM20020I and one microcontroller, a complete communications node
may be implemented.
For more details on the ARCNET protocol engine and traditional dipulse signaling schemes, please refer
to the ARCNET Local Area Network Standard, available from Standard Microsystems Corporation or the
ARCNET Designer's Handbook, available from Datapoint Corporation.
For more detailed information on cabling options including RS485, transformer-coupled RS-485 and Fiber
Optic interfaces, please refer to the following technical note which is available from Standard
Microsystems Corporation: Technical Note 7-5 - Cabling Guidelines for the COM20020I ULANC.
SMSC COM20020I 3.3V
Page 5
Revision 12-06-06
DATASHEET
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