19-4467; Rev 0; 2/09
+3.3V, Low-Jitter, Precision Clock Generator
with Multiple Outputs
General Description
The MAX3629 is a low-jitter precision clock generator
optimized for network applications. The device inte-
grates a crystal oscillator and a phase-locked loop
(PLL) to generate high-frequency clock outputs for
Ethernet applications.
Maxim’s proprietary PLL design features ultra-low jitter
(0.4ps
RMS
) and excellent power-supply noise rejection
(PSNR), minimizing design risk for network equipment.
The MAX3629 contains five LVDS outputs and three
LVCMOS outputs. The output frequencies are selec-
table among 125MHz, 156.25MHz, and 312.5MHz by
pin control.
♦
Crystal Oscillator Interface: 25MHz
♦
OSC_IN Interface:
PLL Enabled: 25MHz
PLL Disabled: 20MHz to 320MHz
♦
Outputs:
One LVDS Output at 125MHz/156.25MHz/
312.5MHz (Selectable with FSELA)
Four LVDS Outputs at 125MHz/156.25MHz/
312.5MHz (Selectable with FSELB)
Three LVCMOS Outputs at 125MHz/156.25MHz
(Selectable with FSELB)
♦
Low Phase Jitter: 0.4ps
RMS
(12kHz to 20MHz)
♦
Excellent PSNR
♦
Operating Temperature Range: 0°C to +70°C
Features
MAX3629
Applications
Ethernet Networking Equipment
Typical Operating Circuit
+3.3V
±5%
Ordering Information
PART
TEMP RANGE
0°C to +70°C
PIN-PACKAGE
32 TQFN-EP*
MAX3629CTJ+
0.1μF
10.5Ω
0.1μF
0.1μF
10μF
V
DDA
0.01μF
V
DD
V
DDO_DIFF
V
DDO_SE
Q0
Z
0
= 50Ω
125MHz/156.25MHz/
312.5MHz
Z
0
= 50Ω
+Denotes
a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
100Ω
ASIC
Q0
Pin Configuration
V
DDO_SE
OSC_IN
MAX3629
33pF
X_OUT
25MHz
(C
L
= 18pF)
X_IN
27pF
Q1
TOP VIEW
GND
Q7
Q6
Q2
Z
0
= 50Ω
125MHz/156.25MHz/
312.5MHz
Z
0
= 50Ω
24
100Ω
ASIC
23
22
21
20
19
18
Q5
17
16
15
14
13
FSELB
RESERVED
Q4
Q4
V
DDO_DIFF
Q3
Q3
GND
Q2
V
DDA
25
PLL_BP 26
Q3
V
DD
PLL_BP
Q3
Z
0
= 50Ω
125MHz/156.25MHz/
312.5MHz
Z
0
= 50Ω
100Ω
ASIC
V
DD
27
FSELA 28
OSC_IN 29
MAX3629
GND
12
11
10
9
8
Q2
Q1
Z
0
= 50Ω
Q4
Z
0
= 50Ω
125MHz/156.25MHz/
312.5MHz
Z
0
= 50Ω
100Ω
ASIC
X_IN 30
X_OUT 31
GND 32
GND, OPEN, OR V
DD
FSELA
Q4
V
DDO_SE
6
V
DDO_DIFF
100Ω
ASIC
RESERVED
Z
0
= 50Ω
125MHz/156.25MHz/
312.5MHz
+
1
Q0
2
Q0
3
GND
4
Q1
5
Q1
*EP
GND, OPEN, OR V
DD
FSELB
33Ω
Q5
125MHz/156.25MHz
Z
0
= 50Ω
ASIC
7
Q2
33Ω
GND
Q6
125MHz/156.25MHz
Z
0
= 50Ω
ASIC
33Ω
Q7
125MHz/156.25MHz
Z
0
= 50Ω
THIN QFN-EP
(5mm
×
5mm)
ASIC
*EXPOSED PAD CONNECTED TO GROUND.
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
+3.3V, Low-Jitter, Precision Clock Generator
with Multiple Outputs
MAX3629
ABSOLUTE MAXIMUM RATINGS
Supply Voltage Range at V
DD
, V
DDA
,
V
DDO_SE
, V
DDO_DIFF ................................................
-0.3V to +4.0V
Voltage Range at Q0,
Q0,
Q1,
Q1,
Q2,
Q2,
Q3,
Q3,
Q4,
Q4,
Q5, Q6, Q7,
PLL_BP,
FSELA, FSELB, OSC_IN .........................-0.3V to (V
DD
+ 0.3V)
Voltage Range at X_IN Pin ....................................-0.3V to +1.2V
Voltage Range at X_OUT Pin
..........................
-0.3V to (V
DD
- 0.6V)
Continuous Power Dissipation (T
A
= +70°C)
32-Pin TQFN-EP (derate 34.5mW/°C above +70°C)..2759mW
Operating Junction Temperature ......................-55°C to +150°C
Storage Temperature Range .............................-65°C to +160°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
DD
= +3.0V to +3.6V, T
A
= 0°C to +70°C, unless otherwise noted. Typical values are at V
DD
= +3.3V, T
A
= +25°C, unless otherwise
noted. When using X_IN, X_OUT input, no signal is applied at OSC_IN. When PLL is enabled,
PLL_BP
= high-Z or high. When PLL is
bypassed,
PLL_BP
= low.) (Note 1)
PARAMETER
Power-Supply Current (Note 2)
SYMBOL
I
DD
PLL enabled
PLL bypassed
CONDITIONS
MIN
TYP
176
160
1.475
0.925
Figure 1
250
400
MAX
224
UNITS
mA
LVDS OUTPUTS (Q0,
Q0,
Q1,
Q1,
Q2,
Q2,
Q3,
Q3,
Q4,
Q4
Pins)
Output High Voltage
Output Low Voltage
Differential Output Voltage
Amplitude
Change in Magnitude of
Differential Output for
Complementary States
Output Offset Voltage
Change in Magnitude of Output
Offset Voltage for
Complementary States
Differential Output Impedance
Output Current
Clock Output Rise/Fall Time
Output Duty-Cycle Distortion
LVCMOS/LVTTL OUTPUTS (Q5, Q6, Q7 Pins)
Output High Voltage
Output Low Voltage
Output Rise/Fall Time
Output Duty-Cycle Distortion
Output Impedance
R
OUT
V
OH
V
OL
t
r
, t
f
I
OH
= -12mA
I
OL
= 12mA
20% to 80% at 125MHz (Note 5)
PLL enabled, PLL bypassed (Note 4)
0.15
45
0.5
50
15
2.6
V
DD
0.4
0.8
55
V
V
ns
%
t
r
, t
f
Shorted together
Short to ground (Note 3)
20% to 80%, R
L
= 100
PLL enabled
PLL bypassed (Note 4)
100
48
46
V
OH
V
OL
|V
OD
|
V
V
mV
|V
OD
|
V
OS
|V
OS
|
80
105
5
8
180
50
50
1.125
25
1.275
25
140
mV
V
mV
mA
330
52
54
ps
%
2
_______________________________________________________________________________________
+3.3V, Low-Jitter, Precision Clock Generator
with Multiple Outputs
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= +3.0V to +3.6V, T
A
= 0°C to +70°C, unless otherwise noted. Typical values are at V
DD
= +3.3V, T
A
= +25°C, unless otherwise
noted. When using X_IN, X_OUT input, no signal is applied at OSC_IN. When PLL is enabled,
PLL_BP
= high-Z or high. When PLL is
bypassed,
PLL_BP
= low.) (Note 1)
PARAMETER
Input-Voltage High
Input-Voltage Low
Input High Current
Input Low Current
SYMBOL
V
IH
V
IL
I
IH
I
IL
V
IN
= V
DD
V
IN
= 0V
PLL enabled
PLL bypassed
(Note 7)
I
IH
I
IL
C
IN
V
IN
= V
DD
V
IN
= 0V
-80
40
50
1.5
625
FSELA = GND
Output Frequency with PLL
Enabled (Q0)
FSELA = V
DD
FSELA = high-Z
FSELB = GND
Output Frequency with PLL
Enabled (Q1 to Q7)
Output Frequency with PLL
Disabled
Integrated Phase Jitter at
125MHz/156.25MHz
Power-Supply Noise Rejection
(Note 11)
Deterministic Jitter Due to
Supply Noise (Note 12)
Nonharmonic and Subharmonic
Spurs
RJ
RMS
FSELB = V
DD
FSELB = high-Z (Note 8)
LVDS outputs
LVCMOS outputs
12kHz to 20MHz,
PLL_BP
= high (Note 9)
12kHz to 20MHz,
PLL_BP
= high-Z
(Note 10)
LVDS output
LVCMOS output
LVDS output
LVCMOS output
(Note 13)
f = 100Hz
f = 1kHz
LVDS Clock Output SSB Phase
Noise at 125MHz (Note 14)
f = 10kHz
f = 100kHz
f = 1MHz
f > 10MHz
20
20
0.4
0.4
-55
-47
9
23
-73
-116
-124
-127
-131
-144
-149
dBc/Hz
ps
RMS
125
156.25
312.5
125
156.25
312.5
320
160
MHz
MHz
MHz
60
20
1.2
-80
25
320
3.6
80
CONDITIONS
MIN
2.0
0
TYP
MAX
V
DD
0.8
80
UNITS
V
V
μA
μA
INPUT SPECIFICATIONS (FSELA, FSELB,
PLL_BP
Pins)
MAX3629
LVCMOS/LVTTL INPUT SPECIFICATIONS (OSC_IN) (Note 6)
Input Clock Frequency
Input Amplitude Range
Input High Current
Input Low Current
Reference Clock Duty Cycle
Input Capacitance
VCO Center Frequency
CLOCK OUTPUT AC SPECIFICATIONS
MHz
MHz
V
μA
μA
%
pF
dBc
ps
P-P
dBc
_______________________________________________________________________________________
3
+3.3V, Low-Jitter, Precision Clock Generator
with Multiple Outputs
MAX3629
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= +3.0V to +3.6V, T
A
= 0°C to +70°C, unless otherwise noted. Typical values are at V
DD
= +3.3V, T
A
= +25°C, unless otherwise
noted. When using X_IN, X_OUT input, no signal is applied at OSC_IN. When PLL is enabled,
PLL_BP
= high-Z or high. When PLL is
bypassed,
PLL_BP
= low.) (Note 1)
PARAMETER
SYMBOL
f = 100Hz
f = 1kHz
LVCMOS Clock Output SSB
Phase Noise at 125MHz
(Note 14)
f = 10kHz
f = 100kHz
f = 1MHz
f > 10MHz
CONDITIONS
MIN
TYP
-115
-124
-126
-130
-144
-151
dBc/Hz
MAX
UNITS
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
Note 14:
A series resistor of up to 10.5Ω is allowed between V
DD
and V
DDA
for filtering supply noise when system power-supply tol-
erance is V
DD
= 3.3V ±5%. See Figure 4.
All outputs unloaded.
The current when an LVDS output is shorted to ground is the steady-state current after the detection circuitry has settled. It
is expected that the LVDS output short to ground condition is short-term only.
Measured with OSC_IN input with 50% duty cycle.
Measured with a series resistor of 33Ω to a load capacitance of 3.0pF. See Figure 2.
The OSC_IN input can be DC- or AC-coupled.
Must be within the absolute maximum rating of V
DD
+ 0.3V.
AC characteristics of LVCMOS outputs (Q5, Q6, and Q7) are only guaranteed up to 160MHz.
Measured with 25MHz crystal (with OSC_IN left open).
Measured with 25MHz reference clock applied to OSC_IN.
Measured at 125MHz output with 40mV
P-P
sinusoidal signal on the supply at 100kHz. Measured with a 10.5Ω resistor
between V
DD
and V
DDA
.
Parameter calculated based on PSNR.
Measurement includes XTAL oscillator feedthrough, crosstalk, intermodulation spurs, etc.
Measured with 25MHz XTAL oscillator.
4
_______________________________________________________________________________________
+3.3V, Low-Jitter, Precision Clock Generator
with Multiple Outputs
MAX3629
Qx
R
L
= 100Ω
Qx
V
V
OD
Qx
SINGLE-ENDED OUTPUT
Qx
IV
OD
I
V
OH
V
OS
V
OL
Qx - Qx
V
ODP-P
= 2IV
OD
I
DIFFERENTIAL OUTPUT
0
Figure 1. Driver Output Levels
V
CC
800Ω
MAX3629
Q5 TO Q7
33Ω
Z
0
= 50Ω
3pF
800Ω
0.1μF
Z
0
= 50Ω
50Ω
50Ω
OSCILLOSCOPE
Figure 2. LVCMOS Output Measurement Setup
_______________________________________________________________________________________
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
