19-4204; Rev 1; 12/08
KIT
ATION
EVALU
BLE
AVAILA
Octal, 12-Bit, 50Msps, 1.8V ADC
with Serial LVDS Outputs
Features
o
Excellent Dynamic Performance
70.2dB SNR at 5.3MHz
98dBc SFDR at 5.3MHz
82dB Channel Isolation at 5.3MHz
o
Ultra-Low Power
96mW per Channel (Normal Operation)
o
Serial LVDS Outputs
o
Pin-Selectable LVDS/SLVS (Scalable Low-Voltage
Signal) Mode
o
LVDS Outputs Support Up to 30in FR-4 Backplane
Connections
o
Test Mode for Digital Signal Integrity
o
Fully Differential Analog Inputs
o
Wide Differential Input Voltage Range (1.4V
P-P
)
o
On-Chip 1.24V Precision Bandgap Reference
o
Clock Duty-Cycle Equalizer
o
Compact, 68-Pin Thin QFN Package with Exposed
Pad
o
Evaluation Kit Available (Order MAX1437BEVKIT)
General Description
The MAX1437B octal, 12-bit analog-to-digital converter
(ADC) features fully differential inputs, a pipelined
architecture, and digital error correction incorporating a
fully differential signal path. This ADC is optimized for
low-power and high-dynamic performance in medical
imaging instrumentation and digital communications
applications. The MAX1437B operates from a 1.8V sin-
gle supply and consumes only 768mW (96mW per
channel) while delivering a 70.2dB (typ) signal-to-noise
ratio (SNR) at a 5.3MHz input frequency. In addition to
low operating power, the MAX1437B features a low-
power standby mode for idle periods.
An internal 1.24V precision bandgap reference sets the
full-scale range of the ADC. A flexible reference struc-
ture allows the use of an external reference for applica-
tions requiring increased accuracy or a different input
voltage range. The reference architecture is optimized
for low noise.
A single-ended clock controls the data-conversion
process. An internal duty-cycle equalizer compensates
for wide variations in clock duty cycle. An on-chip
phase-locked loop (PLL) generates the high-speed ser-
ial low-voltage differential signal (LVDS) clock.
The MAX1437B has self-aligned serial LVDS outputs for
data, clock, and frame-alignment signals. The output
data is presented in two’s complement format.
The MAX1437B offers a maximum sample rate of
50Msps. This device is available in a small, 10mm x
10mm x 0.8mm, 68-pin thin QFN package with exposed
pad and is specified for the extended industrial (-40°C
to +85°C) temperature range.
MAX1437B
Ordering Information
PART
MAX1437BETK+
TEMP RANGE
-40°C to +85°C
PIN-PACKAGE
68 Thin QFN-EP*
Applications
Ultrasound and Medical Imaging
Instrumentation
Multichannel Communications
+Denotes
a lead(Pb)-free/RoHS-compliant package.
*EP
= Exposed pad.
Pin Configuration appears at end of data sheet.
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Octal, 12-Bit, 50Msps, 1.8V ADC
with Serial LVDS Outputs
MAX1437B
ABSOLUTE MAXIMUM RATINGS
AVDD to GND........................................................-0.3V to +2.0V
CVDD to GND........................................................-0.3V to +3.6V
OVDD to GND .......................................................-0.3V to +2.0V
IN_P, IN_N to GND .................................-0.3V to (V
AVDD
+ 0.3V)
CLK to GND ...........................................-0.3V to (V
CVDD
+ 0.3V)
OUT_P, OUT_N, FRAME_,
CLKOUT_ to GND ..............................-0.3V to (V
OVDD
+ 0.3V)
DT, SLVS/LVDS, LVDSTEST, PLL_,
REFIO, REFADJ, CMOUT to GND......-0.3V to (V
AVDD
+ 0.3V)
Continuous Power Dissipation (T
A
= +70°C)
68-Pin Thin QFN 10mm x 10mm x 0.8mm
(derated 70mW/°C above +70°C)..............................4000mW
Operating Temperature Range ...........................-40°C to +85°C
Maximum Junction Temperature .....................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
AVDD
= 1.8V, V
OVDD
= 1.8V, V
CVDD
= 3.3V, V
GND
= 0, external V
REFIO
= 1.24V, C
REFIO
to GND = 0.1µF || 1.0µF, C
REFP
to GND =
10µF, C
REFN
to GND = 10µF, f
CLK
= 50MHz (50% duty cycle), V
DT
= 0, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values
are at T
A
= +25°C.) (Note 1)
PARAMETER
DC ACCURACY (Note 2)
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Gain Error
ANALOG INPUTS (IN_P, IN_N)
Input Differential Range
Common-Mode Voltage Range
Common-Mode Voltage Range
Tolerance
Differential Input Impedance
Differential Input Capacitance
CONVERSION RATE
Maximum Conversion Rate
Minimum Conversion Rate
Data Latency
DYNAMIC CHARACTERISTICS (differential inputs, 4096-point FFT) (Note 2)
Signal-to-Noise Ratio
Signal-to-Noise and Distortion
Effective Number of Bits
Spurious-Free Dynamic Range
SNR
SINAD
ENOB
SFDR
f
IN
= 5.3MHz at -0.5dBFS
f
IN
= 20MHz at -0.5dBFS
f
IN
= 5.3MHz at -0.5dBFS
f
IN
= 20MHz at -0.5dBFS
f
IN
= 5.3MHz at -0.5dBFS
f
IN
= 20MHz at -0.5dBFS
f
IN
= 5.3MHz at –0.5dBFS
f
IN
= 20MHz at -0.5dBFS
79
10.8
67
67
70.2
70.2
70.2
70.1
11.4
11.4
98
93
dB
dB
Bits
dBc
f
SMAX
f
SMIN
50
4.0
6.5
MHz
MHz
Cycles
R
IN
C
IN
V
ID
V
CMO
(Note 3)
Switched capacitor load
Differential input
1.4
0.76
±50
2
12.5
V
P-P
V
mV
kΩ
pF
-3
±0.5
N
INL
DNL
No missing codes over temperature
12
±0.3
±0.25
±2.5
±1
±0.5
+2
Bits
LSB
LSB
%FS
%FS
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
2
_______________________________________________________________________________________
Octal, 12-Bit, 50Msps, 1.8V ADC
with Serial LVDS Outputs
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= 1.8V, V
OVDD
= 1.8V, V
CVDD
= 3.3V, V
GND
= 0, external V
REFIO
= 1.24V, C
REFIO
to GND = 0.1µF || 1.0µF, C
REFP
to GND =
10µF, C
REFN
to GND = 10µF, f
CLK
= 50MHz (50% duty cycle), V
DT
= 0, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values
are at T
A
= +25°C.) (Note 1)
PARAMETER
Total Harmonic Distortion
Intermodulation Distortion
Third-Order Intermodulation
Aperture Jitter
Aperture Delay
Small-Signal Bandwidth
Full-Power Bandwidth
Output Noise
Overrange Recovery Time
INTERNAL REFERENCE
REFADJ Internal Reference-Mode
Enable Voltage
REFADJ Low-Leakage Current
REFIO Output Voltage
Reference Temperature
Coefficient
EXTERNAL REFERENCE
REFADJ External Reference-
Mode Enable Voltage
REFADJ High-Leakage Current
REFIO Input Voltage
REFIO Input Voltage Tolerance
REFIO Input Current
CMOUT Output Voltage
CLOCK INPUT (CLK)
Input High Voltage
Input Low Voltage
Clock Duty Cycle
Clock Duty-Cycle Tolerance
Input Leakage
Input Capacitance
DI
IN
DC
IN
Input at GND
Input at V
AVDD
5
V
CLKH
V
CLKL
50
±30
5
80
0.8 x
V
CVDD
0.2 x
V
CVDD
V
V
%
%
µA
pF
I
REFIO
V
CMOUT
COMMON-MODE OUTPUT (CMOUT)
0.76
V
(Note 4)
V
AVDD
-
0.1V
200
1.24
±5
<1
V
µA
V
%
µA
V
REFIO
TC
REFIO
1.18
(Note 4)
1.5
1.24
120
1.30
0.1
V
mA
V
ppm/°C
t
OR
SYMBOL
THD
IMD
IM3
t
AJ
t
AD
SSBW
LSBW
CONDITIONS
f
IN
= 5.3MHz at -0.5dBFS
f
IN
= 20MHz at -0.5dBFS
f
1
= 5.3MHz at -6.5dBFS
f
2
= 6.3MHz at -6.5dBFS
f
1
= 5.3MHz at -6.5dBFS
f
2
= 6.3MHz at -6.5dBFS
Figure 10
Figure 10
Input at -20dBFS
Input at -0.5dBFS
IN_P = IN_N
R
S
= 25Ω, C
S
= 50pF
MIN
TYP
-96
-93
90.7
98.7
< 0.4
1
100
100
0.44
1
-78
MAX
UNITS
dBc
dBc
dBc
ps
RMS
ns
MHz
MHz
LSB
RMS
Clock
cycle
MAX1437B
_______________________________________________________________________________________
3
Octal, 12-Bit, 50Msps, 1.8V ADC
with Serial LVDS Outputs
MAX1437B
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= 1.8V, V
OVDD
= 1.8V, V
CVDD
= 3.3V, V
GND
= 0, external V
REFIO
= 1.24V, C
REFIO
to GND = 0.1µF || 1.0µF, C
REFP
to GND =
10µF, C
REFN
to GND = 10µF, f
CLK
= 50MHz (50% duty cycle), V
DT
= 0, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values
are at T
A
= +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
0.8 x
V
AVDD
0.2 x
V
AVDD
Input at GND
Input at V
AVDD
5
R
TERM
= 100Ω
R
TERM
= 100Ω
R
TERM
= 100Ω, C
LOAD
= 5pF
R
TERM
= 100Ω, C
LOAD
= 5pF
R
TERM
= 100Ω
R
TERM
= 100Ω
R
TERM
= 100Ω, C
LOAD
= 5pF
R
TERM
= 100Ω, C
LOAD
= 5pF
250
1.125
350
350
205
220
320
320
200
60
1.7
1.7
1.7
f
IN
= 20MHz
at -0.5dBFS
V
STBY
= 0, V
DT
= 0
V
STBY
= 0, V
DT
= 1V
V
STBY
= 1V, no clock input
OVDD Supply Current
I
OVDD
f
IN
= 20MHz
at -0.5dBFS
V
STBY
= 0
V
STBY
= 0, V
DT
= 1V
V
STBY
= 1V, no clock input
CVDD Supply Current
Power Dissipation
I
CVDD
P
DISS
CVDD is used only to bias ESD-protection
diodes on CLK input, Figure 2
f
IN
= 20MHz at -0.5dBFS
1.8
1.8
1.8
348
348
37
74
103
16
0
759
882
100
1.9
1.9
3.5
390
450
1.375
5
80
TYP
MAX
UNITS
DIGITAL INPUTS (PLL_, LVDSTEST, DT, SLVS, STBY)
Input High Threshold
Input Low Threshold
Input Leakage
Input Capacitance
Differential Output Voltage
Output Common-Mode Voltage
Rise Time (20% to 80%)
Fall Time (80% to 20%)
Differential Output Voltage
Output Common-Mode Voltage
Rise Time (20% to 80%)
Fall Time (80% to 20%)
STANDBY MODE (STBY)
STBY Fall to Output Enable
STBY Rise to Output Disable
POWER REQUIREMENTS
AVDD Supply Voltage Range
OVDD Supply Voltage Range
CVDD Supply Voltage Range
AVDD Supply Current
V
AVDD
V
OVDD
V
CVDD
I
AVDD
V
V
V
mA
mA
mA
µA
mA
mW
t
ENABLE
t
DISABLE
µs
ns
V
IH
V
IL
DI
IN
DC
IN
V
OHDIFF
V
OCM
t
RL
t
FL
V
OHDIFF
V
OCM
t
RS
t
FS
V
V
µA
pF
mV
V
ps
ps
mV
mV
ps
ps
LVDS OUTPUTS (OUT_P, OUT_N), SLVS/LVDS = 0
SLVS OUTPUTS (OUT_P, OUT_N, CLKOUTP, CLKOUTN, FRAMEP, FRAMEN), V
SLVS/LVDS
= 1V, V
DT
= 1V
4
_______________________________________________________________________________________
Octal, 12-Bit, 50Msps, 1.8V ADC
with Serial LVDS Outputs
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= 1.8V, V
OVDD
= 1.8V, V
CVDD
= 3.3V, V
GND
= 0, external V
REFIO
= 1.24V, C
REFIO
to GND = 0.1µF || 1.0µF, C
REFP
to GND =
10µF, C
REFN
to GND = 10µF, f
CLK
= 50MHz (50% duty cycle), V
DT
= 0, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values
are at T
A
= +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
(t
SAMPLE
/24)
- 0.15
TYP
MAX
(t
SAMPLE
/24)
+ 0.15
UNITS
MAX1437B
TIMING CHARACTERISTICS (Note 5)
Data Valid to CLKOUT Rise/Fall
CLKOUT Output-Width High
CLKOUT Output-Width Low
FRAME Rise to CLKOUT Rise
Sample CLK Rise to FRAME Rise
Crosstalk
Gain Matching
Phase Matching
C
GM
C
PM
t
OD
t
CH
t
CL
t
CF
t
SF
Figure 5 (Note 6)
Figure 5
Figure 5
Figure 4 (Note 6)
Figure 4 (Note 6)
(Note 2)
f
IN
= 5.3MHz (Note 2)
f
IN
= 5.3MHz (Note 2)
ns
ns
ns
ns
ns
dB
dB
Degrees
t
SAMPLE
/12
t
SAMPLE
/12
(t
SAMPLE
/24)
- 0.15
(t
SAMPLE
/2)
+ 1.1
-75
±0.1
±0.25
(t
SAMPLE
/24)
+ 0.15
(t
SAMPLE
/2)
+ 2.6
Note 1:
Specifications at T
A
≥
+25°C are guaranteed by production testing. Specifications at T
A
< +25°C are guaranteed by design
and characterization and not subject to production testing.
Note 2:
See definition in the
Parameter Definitions
section at the end of this data sheet.
Note 3:
See the
Common-Mode Output (CMOUT)
section.
Note 4:
Connect REFADJ to GND directly to enable internal reference mode. Connect REFADJ to AVDD directly to disable the internal
bandgap reference and enable external reference mode.
Note 5:
Data valid to CLKOUT rise/fall timing is measured from 50% of data output level to 50% of clock output level.
Note 6:
Guaranteed by design and characterization. Not subject to production testing.
Typical Operating Characteristics
(V
AVDD
= 1.8V, V
OVDD
= 1.8V, V
CVDD
= 3.3V, V
GND
= 0, internal reference, differential input at -0.5dBFS, f
IN
= 5.3MHz, f
CLK
=
50MHz (50% duty cycle), V
DT
= 0, C
LOAD
= 10pF, T
A
= +25°C, unless otherwise noted.)
FFT PLOT
(16,384-POINT DATA RECORD)
MAX1437B toc01
FFT PLOT
(16,384-POINT DATA RECORD)
MAX1437B toc02
CROSSTALK
(16,384-POINT DATA RECORD)
MEASURED ON CHANNEL 1,
WITH INTERFERING SIGNAL
ON CHANNEL 2
f
IN(IN1)
= 5.304814MHz
f
IN(IN2)
= 24.0997118MHz
CROSSTALK = -76dB
MAX1437B toc03
0
-10
-20
AMPLITUDE (dBFS)
-30
-40
-50
-60
-70
-80
-90
-100
-110
0
5
10
15
20
HD2
HD3
f
CLK
= 50.1523789MHz
f
IN
= 5.304814MHz
A
IN
= -0.5dBFS
SNR = 69.959dB
SINAD = 69.950dB
THD = -96.635dBc
SFDR = 96.503dBc
0
-10
-20
AMPLITUDE (dBFS)
-30
-40
-50
-60
-70
-80
-90
-100
-110
HD2
HD3
f
CLK
= 50.1523789MHz
f
IN
= 24.0997118MHz
A
IN
= -0.5dBFS
SNR = 69.707dB
SINAD = 69.672dB
THD = -90.672dBc
SFDR = 93.694dBc
10
-10
AMPLITUDE (dBFS)
-30
-50
-70
-90
-110
f
IN(IN2)
25
0
5
FREQUENCY (MHz)
10
15
FREQUENCY (MHz)
20
25
0
5
10
15
20
25
FREQUENCY (MHz)
_______________________________________________________________________________________
5
测试/测量
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