Not Recommended for New Design,
Replace with CAT24C128
CAT24WC128
128K-Bit I
2
C Serial CMOS EEPROM
FEATURES
I
1MHz I
2
C Bus Compatible*
I
1.8 to 6 Volt Operation
I
Low Power CMOS Technology
I
64-Byte Page Write Buffer
I
Self-Timed Write Cycle with Auto-Clear
I
Commercial, Industrial and Automotive
I
Write Protect Feature
H
GEN
FR
ALO
EE
LE
A
D
F
R
E
E
TM
– Entire Array Protected When WP at V
IH
I
100,000 Program/Erase Cycles
I
100 Year Data Retention
I
8-Pin DIP, 8-Pin SOIC or 14-pin TSSOP
I
"Green" Package Options Available
Temperature Ranges
DESCRIPTION
The CAT24WC128 is a 128K-bit Serial CMOS E
2
PROM
internally organized as 16384 words of 8 bits each.
Catalyst’s advanced CMOS technology substantially
reduces device power requirements. The
CAT24WC128 features a 64-byte page write buffer.
The device operates via the I
2
C bus serial interface and
is available in 8-pin DIP, 8-pin SOIC or 14-pin TSSOP
packages.
PIN CONFIGURATION
DIP Package (P, L)
NC
NC
NC
VSS
1
2
3
4
8
7
6
5
VCC
WP
TSSOP Package (U14, Y14)
SCL
VCC
1
14
NC
SDA
NC
WP
13
2
NC
NC
12
3
NC
NC
NC
VSS
4
5
6
7
11
10
9
8
NC
NC
SCL
SDA
BLOCK DIAGRAM
EXTERNAL LOAD
DOUT
ACK
VCC
VSS
WORD ADDRESS
BUFFERS
COLUMN
DECODERS
512
SDA
START/STOP
LOGIC
SENSE AMPS
SHIFT REGISTERS
SOIC Package (J, W, K, X)
NC
NC
NC
VSS
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
XDEC
WP
CONTROL
LOGIC
256
EEPROM
256X512
PIN FUNCTIONS
Pin Name
SDA
SCL
WP
V
CC
V
SS
Function
Serial Data/Address
Serial Clock
Write Protect
+1.8V to +6V Power Supply
Ground
SCL
STATE COUNTERS
HIGH VOLTAGE/
TIMING CONTROL
DATA IN STORAGE
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I
2
C Bus Protocol.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 1038, Rev. E
Not Recommended
CAT24WC128
for New Design,
Replace with CAT24C128
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature ....................... –65°C to +150°C
Voltage on Any Pin with
Respect to Ground
(1)
........... –2.0V to +V
CC
+ 2.0V
V
CC
with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current
(2)
........................ 100mA
RELIABILITY CHARACTERISTICS
Symbol
N
END(3)
T
DR(3)
V
ZAP(3)
I
LTH(3)(4)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-up
Min.
100,000
100
2000
100
Max.
Units
Cycles/Byte
Years
Volts
mA
Reference Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
D.C. OPERATING CHARACTERISTICS
V
CC
= +1.8V to +6.0V, unless otherwise specified.
Limits
Symbol
I
CC1
I
CC2
I
SB(5)
I
LI
I
LO
V
IL
V
IH
V
OL1
V
OL2
Parameter
Power Supply Current - Read
Power Supply Current - Write
Standby Current
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage (V
CC
= +3.0V)
Output Low Voltage (V
CC
= +1.8V)
–1
V
CC
x 0.7
Min.
Typ.
Max.
1
3
1
3
3
V
CC
x 0.3
V
CC
+ 0.5
0.4
0.5
Units
mA
mA
µA
µA
µA
V
V
V
V
I
OL
= 3.0 mA
I
OL
= 1.5 mA
Test Conditions
f
SCL
= 100 KHz
V
CC
=5V
f
SCL
= 100 KHz
V
CC
=5V
V
IN
= GND or V
CC
V
CC
=5V
V
IN
= GND to V
CC
V
OUT
= GND to V
CC
CAPACITANCE
T
A
= 25°C, f = 1.0 MHz, V
CC
= 5V
Symbol
C
I/O(3)
C
IN(3)
Test
Input/Output Capacitance (SDA)
Input Capacitance (SCL, WP)
Max.
8
6
Units
pF
pF
Conditions
V
I/O
= 0V
V
IN
= 0V
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+0.5V, which may overshoot to V
CC
+ 2.0V for periods of less than 20ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V
CC
+1V.
(5) Maximum standby current (I
SB
) = 10µA for the Automotive and Extended Automotive temperature range.
Doc. No. 1038, Rev. E
2
Not Recommended for New Design,
Replace with CAT24C128
A.C. CHARACTERISTICS
V
CC
= +1.8V to +6V, unless otherwise specified
Output Load is 1 TTL Gate and 100pF
Read & Write Cycle Limits
Symbol
Parameter
CAT24WC128
V
CC
=1.8V - 6.0V V
CC
=2.5V - 6.0V V
CC
=3.0V - 5.5V
Min.
Max.
100
0.1
4.7
4.0
4.7
4.0
4.0
0
100
1.0
300
4.7
100
10
0.6
50
10
3.5
0.05
1.2
0.6
1.2
0.6
0.6
0
100
0.3
300
0.25
50
10
Min.
Max.
400
0.9
0.05
0.5
0.25
0.6
0.4
0.25
0
100
0.3
100
Min.
Max.
1000
0.55
Units
kHz
µs
µs
µs
µs
µs
µs
ns
ns
µs
ns
µs
ns
ms
F
SCL
t
AA
t
BUF(1)
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R(1)
t
F(1)
t
SU:STO
t
DH
t
WR
Clock Frequency
SCL Low to SDA Data Out
and ACK Out
Time the Bus Must be Free Before
a New Transmission Can Start
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition Setup Time
(for a Repeated Start Condition)
Data In Hold Time
Data In Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
Write Cycle Time
Power-Up Timing
(1)(2)
Symbol
t
PUR
t
PUW
Parameter
Power-Up to Read Operation
Power-Up to Write Operation
Max.
1
1
Units
ms
ms
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During
the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave
address.
FUNCTIONAL DESCRIPTION
The CAT24WC128 supports the I
2
C Bus data transmis-
sion protocol. This Inter-Integrated Circuit Bus protocol
defines any device that sends data to the bus to be a
transmitter and any device receiving data to be a re-
ceiver. The transfer is controlled by the Master device
which generates the serial clock and all START and
STOP conditions for bus access. The CAT24WC128
operates as a Slave device. Both the Master device and
Slave device can operate as either transmitter or re-
ceiver, but the Master device controls which mode is
activated.
3
Doc. No. 1038, Rev. E
Not Recommended
CAT24WC128
PIN DESCRIPTIONS
for New Design,
Replace with CAT24C128
I
2
C BUS PROTOCOL
The features of the I
2
C bus protocol are defined as
follows:
(1) Data transfer may be initiated only when the bus
is not busy.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes
in the data line while the clock line is high will be
interpreted as a START or STOP condition.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24WC128 monitors
the SDA and SCL lines and will not respond until this
condition is met.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must
end with a STOP condition.
SCL:
Serial Clock
The serial clock input clocks all data transferred into or
out of the device.
SDA:
Serial Data/Address
The bidirectional serial data/address pin is used to
transfer all data into and out of the device. The SDA pin
is an open drain output and can be wire-ORed with
other open drain or open collector outputs.
WP:
Write Protect
This input, when tied to GND, allows write operations to
the entire memory. When this pin is tied to Vcc, the
entire memory is write protected. When left floating,
memory is unprotected.
Figure 1. Bus Timing
tF
tLOW
SCL
tSU:STA
tHD:STA
tHD:DAT
tSU:DAT
tSU:STO
tHIGH
tLOW
tR
SDA IN
tAA
SDA OUT
tDH
tBUF
Figure 2. Write Cycle Timing
SCL
SDA
8TH BIT
BYTE n
ACK
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
Figure 3. Start/Stop Timing
SDA
SCL
START BIT
STOP BIT
Doc. No. 1038, Rev. E
4
Not Recommended for New Design,
Replace with CAT24C128
DEVICE ADDRESSING
The bus Master begins a transmission by sending a
START condition. The Master sends the address of the
particular slave device it is requesting. The seven most
significant bits of the 8-bit slave address are fixed as
1010XXX (Fig. 5), where X can be a 0 or 1. The last bit
of the slave address specifies whether a Read or Write
operation is to be performed. When this bit is set to 1, a
Read operation is selected, and when set to 0, a Write
operation is selected.
After the Master sends a START condition and the slave
address byte, the CAT24WC128 monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address. The
CAT24WC128 then performs a Read or Write operation
depending on the state of the R/W bit.
Acknowledge
After a successful data transfer, each receiving device is
required to generate an acknowledge. The Acknowledg-
ing device pulls down the SDA line during the ninth clock
cycle, signaling that it received the 8 bits of data.
The CAT24WC128 responds with an acknowledge after
receiving a START condition and its slave address. If the
device has been selected along with a write operation,
it responds with an acknowledge after receiving each 8-
bit byte.
When the CAT24WC128 begins a READ mode it trans-
mits 8 bits of data, releases the SDA line, and monitors
the line for an acknowledge. Once it receives this ac-
Figure 4. Acknowledge Timing
SCL FROM
MASTER
CAT24WC128
knowledge, the CAT24WC128 will continue to transmit
data. If no acknowledge is sent by the Master, the device
terminates data transmission and waits for a STOP
condition.
WRITE OPERATIONS
Byte Write
In the Byte Write mode, the Master device sends the
START condition and the slave address information
(with the R/W bit set to zero) to the Slave device. After
the Slave generates an acknowledge, the Master sends
two 8-bit address words that are to be written into the
address pointers of the CAT24WC128. After receiving
another acknowledge from the Slave, the Master device
transmits the data to be written into the addressed
memory location. The CAT24WC128 acknowledges
once more and the Master generates the STOP condi-
tion. At this time, the device begins an internal program-
ming cycle to nonvolatile memory. While the cycle is in
progress, the device will not respond to any request from
the Master device.
Page Write
The CAT24WC128 writes up to 64 bytes of data, in a
single write cycle, using the Page Write operation. The
page write operation is initiated in the same manner as
the byte write operation, however instead of terminating
after the initial byte is transmitted, the Master is allowed
to send up to 63 additional bytes. After each byte has
been transmitted, CAT24WC128 will respond with an
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
Figure 5. Slave Address Bits
1
0
1
0
A2
X
A1
X
A0
X
R/W
X is Don't Care, can be a '0' or a '1'.
5
Doc. No. 1038, Rev. E
微控制器 MCU
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
