Drivers for Large LCD Panels
6bit RSDS
Source Driver
BU95306
No.10043EAT03
TM
●Description
ROHMLCD drivers for large panels are display drivers optimized for large LCDs in a variety of applications, including
desktop PCs, laptops, and TVs. The broad lineup is offered in low amplitude differential transmission interface type
TM
(RSDS ) featuring low EMI, 6bit gradation precision, and different output configurations (642 and up) for wide compatibility.
●Features
1) 600/618/630/642 output channels
TM
2) 6bit 9pair RSDS inputs
3) Dot & n-line inversion available
4) Built-in 2ch repair amplifiers
5)
γ
correction is possible
6) Built-in input data reversing function (INV)
7) Output voltage range : AV
SS
+0.1V~AV
DD
-0.1V
8) High speed data transfer: f
CLK (MAX)
=85MHz
9) Logic power supply voltage (DV
DD
) : 2.3~3.6V
10) Driver power supply voltage (AV
DD
) : 8.0~13.5V
11) Package: COF48
●Applications
TFT LCD Panels
●Line
up matrix
BU95101
Number of outputs
384
BU95303
384 / 414 / 420 / 432
BU95306
600 / 618 / 630 / 642
BU95408
684 / 690 / 702 / 720
www.rohm.com
© 2010 ROHM Co., Ltd. All rights reserved.
1/14
2010.10 - Rev.A
BU95306
●Absolute
maximum ratings
Parameter
Logic power supply voltage
Driver power supply voltage
Logic input voltage
Logic output voltage
Driver input voltage
Driver output voltage
Storage temperature range
Symbol
DV
DD
AV
DD
V
I1
V
O1
V
I2
V
O2
T
stg
Ratings
-0.3 ~ +4.5
-0.3 ~ +14.0
-0.3 ~ DV
DD
+0.3
-0.3 ~ DV
DD
+0.3
-0.3 ~ AV
DD
+0.3
-0.3 ~ AV
DD
+0.3
-55~+125
Unit
V
V
V
V
V
V
℃
Technical Note
●Recommended
Operating Range
Parameter
Logic power supply voltage
Driver power supply voltage
γ-correction
reference voltage
Driver output voltage
Output load capacitance
Maximum clock frequency
Operating temperature range
* AV
SS
=DV
SS
=0V
Symbol
DV
DD
AV
DD
V
0
~V
15
V
O
C
L
f
CLK(MAX)
T
opr
Ratings
+2.3 ~ +3.6
+8.0 ~ +13.5
0.1 ~ AV
DD
-0.1
0.1 ~ AV
DD
-0.1
150
85
-30 ~ +85
Unit
V
V
V
V
pF
MHz
℃
www.rohm.com
© 2010 ROHM Co., Ltd. All rights reserved.
2/14
2010.10 - Rev.A
BU95306
●Electrical
characteristics (DC)
(Unless otherwise noted, Ta=-30~+85℃, DV
DD
=2.3~3.6V, AV
DD
=8.0~13.5V, DV
SS
=AV
SS
=0V)
Limits
Parameter
Symbol
Unit
Conditions
Min.
Typ.
Max.
Logic Part
Logic supply current
Input “H” voltage
Input “L” voltage
Input “H” current
Input “L” current
Input “H” current 2
Input “L” current 2
Output “H” voltage
Output “L” voltage
Driver part
Driver supply current
γ
correction resistance
I
DDA
R
γ
UP
R
γ
LOW
V
OD1*1
-
10.9
10.8
-
-
Output swing voltage
Deviation
Output voltage deviation 2
(between chips)
Repair input voltage
Repair input “H” current
Repair input “L” current
Driver output “H” current
Driver output“L” current
RSDS
TM
input part
RSDS
TM
input “H” voltage
RSDS
TM
input “L” voltage
RSDS
TM
common input
voltage
*1
*2
*3
*4
*5
Technical Note
I
DDL
V
1H
V
1L
I
1H1
I
1L1
I
1H2
I
1L2
V
OH
V
OL
-
0.7DV
DD
0
-
-1
-
-3
DV
DD
-0.5
-
4
-
-
-
-
20
-
-
-
8
DV
DD
0.3DV
DD
+1
-
40
+3
-
0.5
mA
V
V
μA
μA
μA
μA
V
V
DV
DD
=3.3V, Data=00h-3Fh(dot),
fclk=65MHz, fstb=50kHz, 1Line-inverison
R/L,SFTR,INV,SFTL,
POL,STB,SEL0,SEL1,
LPC0,
LPC1 ,TEST0
V
IN
=DV
DD
V
IN
=DV
SS
V
IN
=DV
DD
DV
DD
=3.3V
V
IN
=DV
SS
I
OH
=-1.0mA
SFTR,SFTL
I
OL
=1.0mA
AV
DD
=12V, Data=00h-3Fh(dot),
fclk=65MHz, fstb=50kHz,1Line-inverison,
noLoad, LPC:normal
V0~V7
V8~V15
AV
DD
=12V
Yout=0.1V~1.5V,Yout=10.5V~11.9V
AV
DD
=12V, Yout=1.5V~10.5V
AV
DD
=12V
Yout=0.1V~1.5V,Yout=10.5V~11.9V
AV
DD
=12V, Vout=1.5V~10.5V
AV
DD
=12V, Data=32-gray
Dxx, SFTR, POL, INV,
SFTL,CLK,STB,R/L
SEL0,SEL1,
LPC0,LPC1,TEST0
Built-in Pull down R
9
15.5
15.4
±25
±10
±25
±3
-
-
-
-
-
-
-
-
12
20.2
20.0
-
±25
-
±10
±7.5
AV
DD
-0.1
+1
+1
-0.4
-0.8
-
-
mA
kΩ
kΩ
mV
mV
mV
mV
mV
V
μA
μA
mA
mA
mA
mA
Output voltage deviation
V
RMS*2
V
OD2*3
V
1NB
I
1BH
I
1BL
I
VOHY
I
VOHR
I
VOLY
I
VOLR
-
-
-
0.1
-1
-1
-
-
0.4
0.8
V
IN
=AV
DD
=13.5V
V
IN
=AV
SS
IREP1,2
Y1~Y642, AV
DD
=12V, Vx=6 V,Yout=11V
OREP1,2 ,AV
DD
=12V, Vx=6 V, Yout=11V
Y1~Y642, AV
DD
=12V, Vx=6 V,Yout=1V
OREP1,2 ,AV
DD
=12V, Vx=6 V, Yout=1V
V
IHRSDS
V
ILRSDS
V
CMRSDS
100
-
0.4
200
-200
-
-
-100
DV
DD
-1.2
mV
VCM
RSDS
=+1.2V
*4
mV
V
V
DIFF
=200mV
*5
CLK
P/N
,D
XXP/N
(X=0,1,2)
V
OD1
=measured output voltage - averaged output voltage of all outputs
V
RMS
=measured output swing voltage - averaged output swing voltage of all outputs
V
OD2
=averaged output voltage - target value
VCM
RSDS
= (VCLK
P
+VCLK
N
)/2 or (VD
XXP
+VD
XXN
)/2
V
DIFF
= VCLK
P
- VCLK
N
or VD
XXP
-VD
XXN
www.rohm.com
© 2010 ROHM Co., Ltd. All rights reserved.
3/14
2010.10 - Rev.A
BU95306
●Electrical
characteristics (AC)
(Unless otherwise noted, Ta=-30~+85℃, DV
DD
=2.3~3.6V, AV
DD
=8.0~13.5V, DV
SS
=AV
SS
=0V)
Limits
Parameter
Symbol
Unit
Min.
Typ.
Max.
Clock pulse width
Clock pulse "H" period
Clock pulse "L" period
Data setup time
Data hold time
Start pulse setup time
Start pulse hold time
Start pulse width
Carry output delay time
STB pulse width
Final data timing
tw
th
tl
tsu1
thd1
tsu2
thd2
t
WSFT
tdc
t
WSTB
t
LDT
1/85MHz
5
5
2
0
1
2
1
-
1
1
6
4
14
-
Output delay time
tdout
-
-
-
*1
*2
*3
Technical Note
Conditions
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2
11
-
-
-
-
-
3
5
5
7
ns
ns
ns
ns
ns
ns
ns
CLK period
ns
CLK period
CLK period
CLK period
ns
ns
μs
μs
μs
μs
LPC:normal
LPC:normal
LPC:low power
LPC:low power
*1*3
*2*3
*1*3
*2*3
C
L
=15pF
Time between STB↑and start pulse↑ t
STB-SFT
Time between STB↑and CLK↓
POL/STB setup time
t
STB-CLK
tsp
The value is specified when the drive voltage value reaches the target output voltage level of 90%.
The value is specified when the drive voltage value reaches the target output voltage level of 6-bit accuracy.
Output load condition:
R1=R2=R3=10kΩ, C1=C2=C3=20pF
R1
Output
(Test Probe)
R2
R3
C1
Vcom=AV
SS
C2
C3
www.rohm.com
© 2010 ROHM Co., Ltd. All rights reserved.
4/14
2010.10 - Rev.A
BU95306
●Block
diagram
Technical Note
・・・・・・・・・・・・・・・・・
AV
DD
AV
SS
LPC0,LPC1
OREP1
IREP1
2
Output Buffer
・・・・・・・・・・・・・・・・・
Y640
Y641
Y642
Y1
Y2
Y3
OREP2
IREP2
V0
½V13
POL
14
D/A Converter
6 6 6
6 6 6
・・・・・・・・・・・・・・・・・
Level Shifter
6 6 6
・・・・・・・・・・・・・・・・・
6
6 6
STB
6 6 6
Data Latch
・・・・・・・・・・・・・・・・・
6 6 6
INV
Latch
D
20P/N
½
D
22P/N
RSDS Rx
D
00P/N
½
D
02P/N
D
10P/N
½
D
12P/N
Data Register
214 bit Bi-directional Shift Register
2
CLK
P/N
SFTR
R/L
SEL1, SEL0
DV
DD
DV
SS
SFTL
Fig.1 Block diagram
www.rohm.com
© 2010 ROHM Co., Ltd. All rights reserved.
5/14
2010.10 - Rev.A
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