Advance Information
This document contains information on a product under
development. The parametric information contains target
parameters that are subject to change.
Bt8233
ATM ServiceSAR with xBR Traffic Management
The Bt8233 Service Segmentation and Reassembly Controller integrates ATM terminal
functions, Peripheral Component Interconnect (PCI) Bus Master and Slave controllers, and
a Universal Test and Operation Physical Interface (UTOPIA) interface with service specific
functions in a single package. The
ServiceSAR
Controller generates and terminates Asyn-
chronous Transfer Mode (ATM) traffic and automatically schedules cells for transmission.
The Bt8233 is targeted at 155 Mbit/s throughput systems where the number of Virtual Cir-
cuit Channels (VCCs) is relatively large, or the performance of the overall system is critical.
Examples of such networking equipment include Routers, Ethernet switches, ATM Edge
switches, or Frame Relay switches.
Service Specific Performance
Accelerators
LECID Filtering and Echo Suppression
Dual Leaky Bucket based on CLP
(Frame Relay)
• Frame Relay DE Interworking
• Internal Simple Network Management
Protocol Management Information
Base (SNMP MIB) counters
•
•
Service-Specific Performance Accelerators
The Bt8233 incorporates numerous service-specific features designed to accelerate and
enhance system performance. For example, the Bt8233 implements Echo Suppression of
Local Area Network (LAN) traffic via LAN Emulation Clients (LECID) filtering and supports
Frame Relay Discard Eligibility (DE) to Cell Loss Priority (CLP) interworking.
Flexible Architectures
•
•
•
Multi-peer host
Direct switch attachment via Reverse
UTOPIA
ATM Terminal
– Host control
– Local Bus control
Advanced xBR Traffic Management
•
The xBR Traffic Manager in the Bt8233 supports multiple ATM service categories. This
includes Constant Bit Rate (CBR), Variable Bit Rate (VBR) (both single and dual leaky
bucket), Unspecified Bit Rate (UBR) and Available Bit Rate (ABR). The Bt8233 manages
each VCC independently. It dynamically schedules segmentation traffic to comply with up
to 8+CBR user-configured scheduling priorities for the various traffic classes. Scheduling is
controlled by a schedule table configured by the user and based on a user-specified time
reference. ABR channels are managed in hardware according to user programmable ABR
templates. These templates tune the performance of the Bt8233’s ABR algorithms to the
requirements of a specific system or network.
Optional local processor
xBR Traffic Management (TM)
•
TM4.0 Service Classes
– CBR
– VBR (single, dual & CLP-based leaky
buckets)
– Real time VBR
– ABR
– UBR
– Generic Flow Control (GFC) con-
trolled & uncontrolled flows
Functional Block Diagram
Local Bus
•
•
•
Control/
Status
Timer
Counters
Local
Memory
Interface
Reassembly
Coprocessor
Segmentation
Coprocessor
CBR, VBR,
ABR,UBR
Traffic Manager
•
UTOPIA
Master/Slave
or Bt8222 Cell
Mux ATM
Ace Rx/Tx
Patent
Pending
Multi-client
PCI Bus
PCI
DMA
Master Co-
Slave Processor
•
Cell
FIFO
•
•
Bt8233
8 Levels of priorities (8 + CBR)
Dynamic per-VCC scheduling
Multiple programmable ABR Tem-
plates (supplied by Rockwell or user)
Scheduler driven by local system
clock for low jitter CBR
Internal Resource Management (RM)
Operation and Maintenance (OAM)
cell feedback path
Virtual FIFO Rate Matching (Source
Rate Matching)
Tunnelling
– Virtual Path (VP) Tunnels (Virtual
Channel Identifier (VCI) interleaving
on Protocol Data Units (PDU)
boundaries)
– CBR Tunnels (cells interleaved on
UBR with an aggregate CBR limit)
Multi-Queue Segmentation Processing
The Bt8233’s Segmentation Coprocessor generates ATM cells for up to 64K VCCs at a line rate of up to 200 Mbit/sec for simplex con-
nections. The segmentation coprocessor formats cells on each channel according to segmentation VCC tables, utilizing up to 32 inde-
pendent transmit queues and reporting segmentation status on a parallel set of up to 32 segmentation status queues. The
segmentation coprocessor fetches client data from the host, formats ATM cells while generating and appending protocol overhead,
and forwards these to the UTOPIA port. The segmentation coprocessor operates as a slave to the xBR Traffic Manager which sched-
ules VCCs for transmission.
Multi-Queue Reassembly Processing
The Bt8233’s Reassembly Coprocessor stores the payload data from the cell stream received by the UTOPIA port into host data buff-
ers. Using a dynamic lookup method which supports Network to Network Interface (NNI) or User-Network Interface (UNI) address-
ing, the reassembly coprocessor processes up to 64K VCCs simultaneously. The host supplies free buffers on up to 32 independent
free buffer queues. The reassembly coprocessor performs all Common Part Convergence Sublayer (CPCS) protocol checks and
reports the results of these checks + other status data on 1 of 32 independent reassembly status queues.
High Performance Host Architecture with Buffer Isolation
The Bt8233 host interface architecture maximizes performance and system flexibility. The device’s control and status queues enable
Host/Segmentation Reassembly (SAR) communication via write operations alone. This lowers latency and PCI bus occupancy. Flexi-
bility is achieved by supporting a scalable peer-to-peer architecture. Multiple host clients may be addressed by the SAR as separate
physical or logical PCI peers. Segmentation and reassembly data buffers on the host system are identified by buffer descriptors in
SRC shared (or host) memory which contain pointers to buffers. The use of buffer descriptors in this way allows for isolation of data
buffers from the mechanisms that handle buffer allocation and linking. This provides a layer of indirection in buffer assignment and
management that maximizes system architecture flexibility.
Designer Toolkit
Rockwell provides an evaluation system for the Bt8233, which provides a working reference design, an example software driver, and
facilities for generating and terminating all service categories of ATM traffic. This system accelerates ATM system development by
providing a rapid prototyping environment.
Copyright © 1997 Rockwell Semiconductor Systems, Inc. All rights reserved.
Print date: October 1997
Rockwell Semiconductor Systems, Inc. reserves the right to make changes to its products or specifications to improve performance,
reliability, or manufacturability. Information furnished is believed to be accurate and reliable. However, no responsibility is
assumed for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by its implication or otherwise under any patent or intellectual property rights of Rockwell Semiconductor Systems, Inc.
Rockwell Semiconductor Systems, Inc. products are not designed or intended for use in life support appliances, devices, or systems
where malfunction of a Rockwell Semiconductor Systems, Inc. product can reasonably be expected to result in personal injury or
death. Rockwell Semiconductor Systems, Inc. customers using or selling Rockwell Semiconductor Systems, Inc. products for use
in such applications do so at their own risk and agree to fully indemnify Rockwell Semiconductor Systems, Inc. for any damages
resulting from such improper use or sale.
Bt is a registered trademark of Rockwell Semiconductor Systems, Inc. SLC
®
is a registered trademark of AT&T Technologies, Inc.
Product names or services listed in this publication are for identification purposes only, and may be trademarks or registered
trademarks of their respective companies. All other marks mentioned herein are the property of their respective holders.
Specifications are subject to change without notice.
PRINTED IN THE UNITED STATES OF AMERICA
Detailed Feature Summary
Multi-Queue Segmentation
Processing
32 Transmit queues with optional priority
levels
• 64K VCCs maximum
(1)
• ATM Adaptation Layer (AAL5) CPCS gen-
eration
• AAL0 Null CPCS (optional use of PTI
for PDU demarcation)
• ATM cell header generation
• Raw cell mode (52 octet)
• 200 MBit/sec half duplex
• 155 MBit/sec full duplex (w/ 2-cell PDUs)
• Variable length transmit First In First Out
(FIFO) - Cell Delay Variation (CDV) - Host
latency matching (1 to 9 cells)
• Symmetric Tx and Rx architecture
– Buffer descriptors
– Queues
Statistics and Write-Only
Counters
•
Global register counter of # of cells
transmitted
• Global register counter of # of cells
received on active channels
• Global T register counter of # of cells
received on inactive channels
• Global register counter of # of AAL5
CPCS-PDUs discarded due to per-channel
firewall, etc
• Reassembly (Rsm) per-VCC Service Dis-
card counters (Frame Relay & LAN Emu-
lation (LANE))
• One programmable interval timer (32 bits
w/ interrupt)
Designer Toolkit
•
•
•
Evaluation System (Bt8233 EVS)
Reference schematics
Hardware Programming Interface -
Bt8233HPI reference Source code (C)
•
Multi-Queue Reassembly
Processing
•
•
•
•
32 reassembly queues
64K VCCs maximum
(1)
AAL5 CPCS Checking
AAL0
– Payload Type Identifier (PTI) Termina-
tion
– Cell Count Termination
High Performance Host Architec-
ture with Buffer Isolation
•
•
Write-Only Control and Status
Read Multiple command for data
transfer
• Up to 32 Host Clients Control and
Status Queues
• Physical or logical clients
– Enables peer-to-peer architecture
•
Early Packet Discard (EPD), based on:
Receive buffer underflow
Receive status overflow
CLP with priority threshold
AAL5 max PDU length
Rx FIFO full
Frame Relay DE with priority
threshold
– LECID Filtering and Echo
Suppression
– Per-VCC firewalls
–
–
–
–
–
–
•
•
•
•
•
•
•
User defined field circulates back to the
host (32 bits)
Distributed host or SRC shared memory
segmentation
Simultaneous segmentation and
reassembly
Per-PDU control of CLP/PTI (UBR)
Per-PDU control of AAL5 UU field
Message & Streaming Status Modes
Virtual Tx FIFO (PCI host)
•
•
•
•
•
•
•
•
Generous Implementation of
OAM-PM Protocols
•
•
•
•
Detection of all F4/F5 OAM flows
Internal PM monitoring and generation
for up to 128 VCCs
Optional Global OAM Rx/Tx Queues
In-Line OAM insertion & generation
Standards Compliance
•
•
•
•
•
•
•
•
•
User Network Interface/Network to Net-
work Interface (UNI/NNI) 3.1
TM 4.0
I.363
I.610 /GR-1248
AToM MIB (RFC1695)
Interim Local Management Interface
(ILMI) MIB
American National Standards Institute
(ANSI) T1.635
GFC per I.361
SNMP
Descriptor-based buffer chaining
Scatter/Gather Direct Memory Access
(DMA)
Endian Neutral
Non-word (byte) aligned host buffer
addresses
Automatically detects presence of Tx data
or Rx free buffers
Virtual FIFOs (PCI bursts treated as a sin-
gle address)
Hardware indication of Beginning of Mes-
sage (BOM)
Allows isolation of system resources
•
Dynamic channel lookup (NNI or UNI
addressing)
–
–
–
–
Supports full address space
Deterministic
Flexible VCI count per VPI
Optimized for signalling address
assignment
•
•
•
•
•
•
Standards-Based I/O
•
•
33 MHz PCI 2.0
Physical Layer (PHY) Interfaces
– UTOPIA Master (Level 1)
– UTOPIA Slave (Level 1)
– Bt8222 Cell Mux
•
•
•
•
•
•
•
•
•
•
Flexible local memory architecture
Optional local control interface
Boundary Scan for board-level testing
Source loopback, for diagnostics
Glueless connection to Bt8222 ATM phys-
ical layer device
Message and Streaming Status Modes
Raw cell mode (52 octet)
200 MBit/sec half duplex
155 MBit/sec full duplex (w/ 2-cell
PDUs)
Distributed host or SRC shared memory
reassembly
Eight programmable reassembly hard-
ware time-outs (per-VCC assignable)
Global max PDU length for AAL5
Per-VCC buffer Firewall (memory usage
limit)
Simultaneous reassembly and
segmentation
Idle cell filtering
32K ABR VCCs
Electrical/Mechanical
•
•
•
•
•
•
208 pin Plastic Quad Flat Pack (PQFP)
Pin-compatible with Bt8230 SRC
Low Power 1.5 W (typical) @ full rate
Industrial temperature range
TTL level inputs
Complementary Metal-Oxide Semicon-
ductor (CMOS) level outputs
Note: (1) Depends on SRC shared memory size and device configuration.
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