BU-61703/61705
SIMPLE SYSTEM RT (SSRT)
DESCRIPTION
The BU-61703/5 Simple System RT
(SSRT) MIL-STD-1553 terminals provide
a complete interface between a simple
system and a MIL-STD-1553 bus. These
terminals integrate dual transceiver,
protocol logic, and a FIFO memory for
received messages in a 1.0 inch square
ceramic package. The SSRT provides
multi-protocol support of MIL-STD-
1553A/B, MIL-STD-1760, McAir, and
STANAG-3838.
The SSRT's transceivers are completely
monolithic, require only a +5V supply, and
consume low power. There are versions
of the simple system RT available with
transceivers trimmed for MIL-STD-1760
compliance, or compatible to McAir stan-
dards. As a means of further reducing
power consumption, the SSRT is avail-
able in versions with its logic powered by
+3.3V, or +5V. The SSRT can operate
with a choice of clock frequencies of 10,
12, 16, or 20 MHz.
The SSRT is ideal for stores and other
simple systems that do not require a
microprocessor. To streamline the inter-
face to simple systems, the SSRT
includes an internal 32-word FIFO for
received data words. This serves to
ensure that only complete, consistent
blocks of validated data words are trans-
ferred to a system.
The SSRT incorporates a built-in self-test
(BIT).This BIT, which is processed follow-
ing power turn-on or after receipt of an
Initiate self-test mode command, pro-
vides a comprehensive test of the SSRT's
encoders, decoders, protocol, transmitter
watchdog timer, and protocol. The result
of the built-in test may be conveyed to the
bus controller by means of the SSRT's
Terminal Flag bit and/or its RT BIT word.
The SSRT includes an auto-configuration
feature. This may be used to enable the
SSRT to run (or not run) its BIT at power
turn-on, to select between MIL-STD-
1553A or -1553B protocol, to transfer
received data words to a system either
individually or by means of a burst trans-
fer, to implement wraparound for subad-
dress 30 (per MIL-STD-1553B Notice 2),
along with options involving the reporting
of self-test failures and loopback errors.
FEATURES
•
Complete Integrated Remote
Terminal Including:
Dual Low-Power 5V Only Transceiver
Complete RT Protocol Logic
STANAG-3838 RT, and
MIL-STD-1760 Stores Management
•
Supports MIL-STD-1553A/B Notice 2,
•
1.0 X 1.0 Inch, 72-pin Package
•
Choice of 5V or 3.3V Logic Power
•
Meets 1553A/McAir Response Time
Requirements
•
Internal FIFO for Burst Mode
Capability on Receive Data
•
16-bit DMA Interface
•
Auto Configuration Capability
•
Comprehensive Built-in Self-test
•
Direct Interface to Simple
(Processorless) Systems
10, 12, 16, or 20 MHz
•
Selectable Input Clock:
55Ω
BUS A
55Ω
TRANSMITTER
INHIBIT
TX_INH
55Ω
BUS B
55Ω
B-3226
B-3227
TX/RX A
TRANSCEIVER
A
DATA
BUFFERS
DMA
HANDSAKE
AND
TRANDFER
CONTROL
LOGIC
D15-D0
DTREQ
DTGRT
DTACK
HS FAIL
MEMOE
MEMWR
SYSTEM
DATA
TX/RX A
TX/RX B
TRANSCEIVER
B
DMA
HANDSAKE
CONTROL
TX/RX B
B-3226
B-3227
MSTCLR
DATA
TRANSFER
CONTROL
CONTROL
INPUTS
AUTO_CFG
BRO_ENA
DUAL
ENCODER
DECODER
AND
RT STATE
LOGIC
L_BRO, T/R, SA4-SA0
WC/MC/CWC4-0
COMMAND
ADDRESS
BUS
ILLEGAL
RTAD4-RTAD0
SRV_RQST
SSFLAG
BUSY
RTACTIVE
INCMD
RT
ADDRESS
RTADP
RT_AD_LAT
RT_AD_ERR
RT
WORD
INPUTS
CLK_IN
GBR
MSG_ERR
RTFAIL
CLOCK
FEQUENCEY
SELECTION
CLK_SEL1
CLK_SEL0
RT
MESSAGE
STATUS
FIGURE 1. BU-61703/5 BLOCK DIAGRAM
©
2000 Data Device Corporation
TABLE 1. SIMPLE SYSTEM RT SPECIFICATIONS
PARAMETER
ABSOLUTE MAXIMUM RATING
Supply Voltage
n
Logic +5V or +3.3V
n
RAM +5V
n
Transceiver +5V
n
Voltage Input Range for +5V
Powered Logic (BU-61705)
n
Voltage Input Range for +3.3V
Powered Logic (BU-61703)
RECEIVER
Differential Input Resistance
(Notes 1-6)
Differential Input Capacitance
(Notes 1-6)
Threshold Voltage, Transformer
Coupled,
Common Mode Voltage (Note 7)
TRANSMITTER
Differential Output Voltage
n
Direct Coupled Across 35
Ω,
Measured on Bus
n
Transformer Coupled Across
70
Ω,
Measured on Bus
BU-61573(5)XX-XX0 (Note 8)
BU-61573(5)XX-XX2
(Note 8, 9,13)
Output Noise, Differential (Direct
Coupled)
Output Offset Voltage, Transformer
Coupled Across 70 ohms
Rise/Fall Time
BU-61703(5)X3
BU-61703(5)X4
LOGIC
V
IH
All signals except CLK_IN
CLK_IN
V
IL
All signals except CLK_IN
CLK_IN
Schmidt Hysteresis
All signals except CLK_IN
CLK_IN
I
IH
(Vcc=5.5V, V
IN
=Vcc)
I
IH
(Vcc=5.5V, V
IN
=2.7V)
I
IH
(Vcc=3.6V, V
IN
=Vcc)
I
IH
(Vcc=3.6V, V
IH
=2.7V)
I
IL
(Vcc=5.5V, V
IH
=0.4V)
I
IL
(Vcc=3.6V, V
IH
=0.4V)
V
OH
(Vcc=4.5V, V
IH
=2.7V,
V
IL
=0.2V, I
OH
=max)
V
OH
(Vcc=3.0V, V
IH
=2.7V,
V
IL
=0.2V, I
OH
=max)
V
OL
(Vcc=4.5V, V
IH
=2.7V,
V
IL
=0.2V, I
OL
=max)
V
OL
(Vcc=3.0V, V
IH
=2.7V,
V
IL
=0.2V, I
OL
=max)
I
OL
I
OH
C
I
(Input Capacitance)
C
IO
(Bi-directional signal input
capacitance)
MIN
TYP
MAX
UNITS
TABLE 1. SIMPLE SYSTEM RT SPECIFICATIONS (Cont’d)
PARAMETER
POWER SUPPLY REQUIREMENTS
Voltages/Tolerances
n
+5V Logic (BU-61705) (Note 10)
n
+3.3V Logic (BU-61703) (Note 10)
n
+5V Ch. A, +5, Ch. B (Note 10)
Current Drain
n
BU-61705
n
+5V (transceiver, logic)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
n
BU-61703
n
+5V (transceiver)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
n
3.3V Logic
POWER DISSIPATION
Total Hybrid
n
BU-61705
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
n
BU-61703
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
Hottest Die
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
CLOCK INPUT
Frequency
n
Nominal Value
• Default
• Option
• Option
• Option
n
Long Term Tolerance
• 1553A Compliance
• 1553B Compliance
n
Short Term Tolerance, 1 second
• 1553A Compliance
• 1553B Compliance
n
Duty Cycle
1553 MESSAGE TIMING
RT-to-RT Response Timeout
(Note 12)
RT Response Time
(mid-parity to mid-sync) (Note 12)
Transmitter Watchdog Timeout
THERMAL
Thermal Resistance, Junction-to-Case,
Hottest Die (θ
JC
)
Operating Junction Temperature
Storage Temperature
Lead Temperature (soldering, 10 sec.)
MIN
TYP
MAX
UNITS
-0.3
-0.3
-0.3
-0.3
-0.3
2.5
6.0
6.0
7.0
6.0
6.0
V
V
V
V
V
KΩ
4.5
3.0
4.75
5.0
3.3
5.0
5.5
3.6
5.5
V
V
V
140
240
340
540
mA
mA
mA
mA
5
0.200
0.860
10
pF
Vp-p
Vpeak
80
180
280
480
40
mA
mA
mA
mA
mA
6
7
9
Vp-p
18
20
20
22
27
27
10
Vp-p
Vp-p
M
V
P
-
P
0.77
0.97
1.17
1.57
0.58
0.78
0.98
1.38
0.22
0.42
0.62
1.02
W
W
W
W
W
W
W
W
W
W
W
W
-250
150
250
mV
peak
100
200
150
250
300
300
nsec
nsec
2.1
0.8•Vcc
0.7
0.2•Vcc
0.4
1.0
-10
-350
-10
-350
-350
-350
2.4
2.4
0.4
0.4
3.4
-3.4
50
50
V
V
V
V
V
V
µA
µA
µA
µA
µA
µA
V
V
V
V
mA
mA
pF
pF
16.0
12.0
10.0
20.0
-0.01
-0.10
0.001
-0.01
40
0.01
0.1
0.001
0.01
60
MHz
MHz
MHz
MHz
%
%
%
%
%
10
-50
10
-33
-50
-33
17.5
4
18.5
19.5
7
µs
µs
µs
660.5
-55
-65
20
150
150
+300
°C/W
°C
°C
°C
2
TABLE 1. SIMPLE SYSTEM RT SPECIFICATIONS (Cont’d)
PARAMETER
PHYSICAL CHARACTERISTICS
Size
1.0 X 1.0 X 0.155
(25.4 x 25.4 x 3.94)
Weight
0.6
(17)
NOTES:
Notes 1 through 6 are applicable to the Receiver Differential Resistance
and Differential Capacitance specifications:
(1)
Specifications include both transmitter and receiver (tied together
internally).
Impedance parameters are specified directly between pins
TX/RX A(B) and
TX / RX A(B)
of the SSRT hybrid.
It is assumed that all power and ground inputs to the hybrid are con-
nected.
The specifications are applicable for both unpowered and powered
conditions.
The specifications assume a 2 volt rms balanced, differential, sinu-
soidal input. The applicable frequency range is 75 kHz to 1 MHz.
Minimum resistance and maximum capacitance parameters are
guaranteed over the operating range, but are not tested.
Assumes a common mode voltage within the frequency range of dc
to 2 MHz, applied to the pins of the isolation transformer on the stub
side (either direct or transformer coupled), and referenced to hybrid
ground. Transformer must be a DDC recommended transformer or
other transformer that provides an equivalent minimum CMRR.
An "X" in one or more of the product type fields indicates that the ref-
erence is applicable to all available product options.
MIL-STD-1760 requires an output of 20 Vp-p minimum on the stub
connection.
oz
(g)
in.
(mm)
MAX
UNITS
INTRODUCTION
GENERAL
The BU-61703/5 Simple System RT (SSRT) is a complete MIL-
STD-1553 Remote Terminal (RT) bus interface unit. Contained in
this hybrid are a dual transceiver and Manchester II
encoder/decoder, and MIL-STD-1553 Remote Terminal (RT) pro-
tocol logic. Also included are built-in self-test capability and a
parallel subsystem interface. The subsystem interface includes a
12-bit address bus and a 16-bit data bus that operates in a 16-
bit DMA handshake transfer configuration. The local bus and
associated control signals may be operated from either +5 volt or
+3.3 volt power.
The transceiver front end of the BU-61703/5 is implemented by
means of low-power monolithic technology. The transceiver
requires only a single +5 V voltage source. The voltage source
transmitters provide superior line driving capability for long
cables and heavy amounts of bus loading. In addition, the mono-
lithic transceivers provide a minimum stub voltage level of 20
volts peak-to-peak transformer coupled, making the BU-61703/5
suitable for MIL-STD-1760 applications.
The receiver sections of the BU-61703/5 are fully compliant with
MIL-STD-1553B in terms of front-end overvoltage protection,
threshold, and bit-error rate.
The BU-61703/5 implements all MIL-STD-1553 message for-
mats, including all 13 MIL-STD 1553 dual redundant mode
codes. Any subset of the possible 1553 commands (broadcast,
T/R bit, subaddress, word count/mode code) may be optionally
illegalized by means of an external PROM, PLD, or RAM. An
extensive amount of message validation is performed for each
message received. Each word received is validated for correct
sync type and sync encoding, Manchester II encoding, parity,
and bit count. All messages are verified to contain a legal,
defined command word and correct word count. If the BU-
61703/5 is the receiving RT in an RT-to-RT transfer, it verifies
that the T/R bit of the transmit command word is logic "1" and
that the transmitting RT responds in time and contains the cor-
rect RT address in its Status Word.
The BU-61703/5 may be operated from a 10, 12, 16, or 20 MHz
clock input. For any clock frequency, the decoder samples
incoming data on
both
edges of the clock input. This oversam-
pling, in effect, provides for a sampling rate of twice the input
clocks' frequency. Benefits of the higher sampling rate include a
wider tolerance for zero-crossing distortion and improved bit
error rate performance.
The BU-61703/5 includes a hardwired R.T. address input. This
includes 5 address lines, an address parity input, and an
address parity error output. The RT address can also be latched
by means of a latching input signal.
The BU-61703/5 supports command illegalization. Commands
may be illegalized by asserting the input signal
ILLEGAL
active
low within approximately 2 µs after the mid-parity bit zero-cross-
ing of the received command word. Command words may be ille-
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10) External 10 µF tantalum and 0.1 µF capacitors to ground should be
located as close as possible to Pins 20 and 72, and a 0.1 µF capac-
itor at pin 37.
(11) Power dissipation specifications assume a transformer coupled con-
figuration, with external dissipation (while transmitting) of 0.14 watts
for the active isolation transformer, 0.08 watts for the active bus cou-
pling transformer, 0.45 watts for each of the two bus isolation resis-
tors, and 0.15 watts for each of the two bus termination resistors.
(12) Measured from mid-parity crossing of command word to mid-sync
crossing of RT's status word.
(13) MIL-STD-1760 compliant output voltage not available for
BU-61703/5X4 versions.
3
galized as a function of broadcast,
T / R
bit, subaddress, word
count, and/or mode code.
An internal Built-in-Test (BIT) Word register is updated at the end
of each message. The contents of the BIT Word Register are
transmitted in response to a Transmit BIT Word Mode Command.
The BU-61703/5 provides a number of real-time output signals.
These various signals provide indications of message in
progress, valid received message, message error, handshake
fail, loop-test fail or transmitter timeout.
The BU-61703/5 includes standard DMA handshake signals
(Request, Grant, and Acknowledge) as well as transfer control
outputs (
MEMOE
and
MEMWR
). The DMA interface operates in
a 16-bit mode, supporting word-wide transfers.
The SSRT's system interface allows the BU-61703/5 to be inter-
faced directly to a simple system that doesn't include a micro-
processor. This provides a low-cost 1553 interface for A/D and
D/A converters, switch closures, actuators, and other discrete
I/O signals.
The BU-61703/5 has an internal FIFO for received data words.
This 32-word deep FIFO may be used to allow the BU-61703/5
to transfer its data words to the local system in burst mode. Burst
mode utilizes the FIFO by transferring data to the local bus at a
rate of one data word every three clock cycles. Burst mode nego-
tiates only once for use of the subsystem bus. Negotiation is per-
formed only after all 1553 data words have been received and
validated. In non-burst mode, the BU-61703/5 will negotiate for
the local bus after every received data word. The data word
transfer period is three clock cycles for each received 1553 data
word.
The BU-61703/5 may also be used in a shared RAM interface
configuration. By means of tri-state buffers and a small amount
of "glue" logic, the BU-61703/5 will store Command Words and
access Data Words to/from dedicated "mailbox" areas in a
shared RAM for each broadcast / T/R bit / subaddress / mode
code.
puts may be used to map into 4K words of processor address
space. The BU-61703/5's addressing scheme maps messages
in terms of broadcast/own address, transmit/receive, subad-
dress, and word/count mode code. A 32-word message block is
allocated for each T/R-subaddress.
For non-mode code messages, the Data Words to be transmit-
ted or received are accessed from (to) relative locations 0
through 31 within the respective message block. For the MIL-
STD-1553B Synchronize with data, Selected transmitter shut-
down, Override selected transmitter shutdown, and Transmit vec-
tor word mode commands which involve a single data word
transfer, the address for the data word is offset from location 0 of
the message block for subaddresses 0 and 31 by the value of the
mode code field of the received command word.
The data words transmitted in response to the Transmit last
command or Transmit BIT word mode commands are accessed
from a pair of internal registers.
DMA INTERFACE
A 16-bit data bus, a 12-bit address bus, and six control signals
are provided to facilitate communication with the parallel sub-
system. The data bus D15-D0 consists of bi-directional tri-state
signals. The address bus L_BRO,
T / R
, SA4-SA0, and
WC/MC/CWC4-0; along with the data transfer control signals
MEMOE
and
MEMWR
are two-state output signals.
The control signals include the standard DMA handshake sig-
nals
DTREQ
,
DTGRT
,
DTACK
, as well as the transfer control
outputs
MEMOE
and
MEMWR
.
HS _ FAIL
provides an indication
to the subsystem of a handshake failure condition.
Data transfers between the subsystem and the BU-61703/5 are
performed by means of a DMA handshake, initiated by the BU-
61703/5. A data read operation is defined to be the transfer of
data from the subsystem to the BU-61703/5. Conversely, a data
write operation transfers data from the BU-61703/5 to the sub-
system. Data is transferred as a single 16-bit word
ADDRESS MAPPING:
DMA READ OPERATION
A typical addressing scheme for the BU-61703/5 12-bit address
bus could be as follows:
In response to a transmit command, the BU-61703/5 needs to
read data words from the external subsystem. To initiate a data
word read transfer, the SSRT asserts the signal
DTREQ
low.
Assuming that the subsystem asserts
DTGRT
in time, the SSRT
will then assert the appropriate values of L_BRO (logic "0"),
T / R
(high), SA4-0, and MC/CWC4-0;
MEMWR
high, along with
DTACK
low and
MEMOE
low to enable data to be read from the
subsystem.
After the transfer of each Data Word has been completed, the
value of the address bus outputs CWC4 through CWC0 is incre-
mented.
A11:
A10:
A9-A5:
A4-A0:
BROADCAST / OWNADDRESS
TRANSMIT/ RECEIVE
SUBADDRESS 4-0
WORD COUNT/MODE CODE 4-0
This method of address mapping provides for a "mailbox" allo-
cation scheme for the storage of data words. The 12 address out-
4
DMA WRITE OPERATION
In response to a receive command, the BU-61703/5 will need to
transfer data to the subsystem. There are two options for doing
this, the burst mode and the non-burst mode. In burst mode,
all
received data words are transferred from the SSRT to the sub-
system in a contiguous burst, only following the reception of the
correct number of valid data words. In the non-burst mode,
single
data words are written to the external subsystem imme-
diately following the reception of each individual data word.
To initiate a DMA write cycle, the SSRT asserts
DTREQ
low. The
subsystem must then respond with
DTGRT
low. Assuming that
DTGRT
was asserted in time, the BU-61703/5 will then assert
DTACK
low. The BU-61703/5 will then assert the appropriate
value of L_BRO,
T / R
, SA4-0, and MC/CWC4-0,
MEMOE
high,
and
MEMWR
low.
MEMWR
will be asserted low for one clock
cycle. The subsystem may then use either the falling or rising
edge of
MEMWR
to latch the data. Similar to the DMA read oper-
ation, the address outputs CWC4 through CWC0 are increment-
ed after the completion of a DMA write operation.
RT ADDRESS
RT Address 4-0 (RT_AD_4 = MSB) and RT Address Parity
(RT_AD_P) should be programmed for a unique RT address and
reflect an odd parity sum. The BU-61703/5 will not respond to
any MIL-STD-1553 commands or transfer received data from
any non-broadcast messages if an odd parity sum is not pre-
sented by RT_AD_4-0 and RT_AD_P. An address parity error will
be indicated by a low output on the
RT_AD_ERR
pin. The input
signal RT_AD_LAT operates a transparent latch for RTAD4-
RTAD0 and RTADP. If RT_AD_LAT is low, the output of the latch
tracks the value presented on the input pins. If RT_AD_LAT is
high, the output of the internal latch becomes latched to the val-
ues presented at the time of a low-to-high transition of
RT_AD_LAT.
RT address and RT Address Parity
must
be presented valid
before the mid-parity crossing of the 1553 command and held, at
least, until following the first received data word.
COMMAND ILLEGALIZATION
HANDSHAKE FAIL
Following the assertion of
DTREQ
low by the SSRT, the external
subsystem has 10 µs to respond by asserting
DTACK
to logic
"0".
If the BU-61703/5 (SSRT) asserts
DTREQ
and the subsystem
does not respond with
DTGRT
in time for the BU-61703/5 to
complete a data word transfer, the
HSFAIL
output will be assert-
ed low to inform the subsystem of the handshake failure, and bit
12 in the internal Built-In-Test (BIT) word will be set to logic "1."
If the handshake failure occurs on a data word read transfer (for
a transmit command), the SSRT will abort the current message
transmission. In the case of a handshake failure on a write trans-
fer (received command) the SSRT will set the handshake failure
output and BIT word bit, and abort processing the current mes-
sage.
The BU-61703/5 includes a provision for command illegalization.
If a command is illegalized, the BU-61703/5 will set the Message
error bit and transmit its status word to the Bus Controller. No
data words will be transmitted in response to an illegalized trans-
mit command. However, data words associated with an illegal-
ized receive command
will
be written to the external subsystem
(although these transfers may be blocked using external logic).
ILLEGAL
is sampled approximately 2 µs following the mid-parity
bit zero crossing of the received command word. A low on
ILLEGAL
will illegalize a particular command word and cause the
SSRT to respond with its Message error bit set in its status word.
Command illegalization based on broadcast,
T / R
bit, subad-
dress, and/or word count/mode code may be implemented by
means of an external PROM, PLD, or RAM device, as shown in
Figure 2.
The external device may be used to define the legality of specif-
ic commands. Any subset of the possible 1553 commands may
be illegalized as a function of broadcast,
T / R
bit, subaddress,
word count, and/or mode code. The output of the illegalization
device should be tied directly to the BU-61703/5's
ILLEGAL
sig-
nal input. The maximum access time of the external illegalizing
device is 400 ns.
If illegalization is not used,
ILLEGAL
should be hardwired to logic
"1".
MESSAGE PROCESSING OPERATION
Following the receipt and transfer of a valid Command Word, the
BU-61703/5 will attempt to perform one of the following opera-
tions: (1) transfer received 1553 data to the subsystem, (2) read
data from the subsystem for transmission on the 1553 bus, (3)
transmit status (and possibly the last command word or RT BIT
word) on the 1553 bus, and/or (4) set status word conditions.
The BU-61703/5 responds to all non-broadcast messages to its
RT address with a 1553 Status Word.
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
